New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for HEP detectors at HL-LHC

Paterno, A.; Pacher, L.; Demaria, N.; Rivetti, A.; Dellacasa, G.; Marconi, S.; Placidi, P.

doi:10.1109/nssmic.2016.8069855

Cited by 5 publications

(5 citation statements)

References 13 publications

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“…A novel region-based digital architecture [9] for latency buffering and trigger matching, able to withstand extended trigger latencies and unprecedented data rates at HL-LHC, has been studied and implemented. Pixels are grouped in pixel regions (PR) made of 4×4 pixels, as illustrated in Fig.…”

Section: B Region Digital Architecturementioning

confidence: 99%

“…A novel digital architecture [9] has been designed in order to maintain a high efficiency (above 99%) at pixel hit rates up to 3 GHz/cm 2 , trigger rates up to 1 MHz with a trigger latency up to 12.5 µs. The digital architecture is organized in pixel regions (PR), where the hit is stored locally and which is transmitted to the end of column only in the case of an external trigger signal.…”

Section: Introductionmentioning

confidence: 99%

“…Charge information is retrieved from pixels using 5-bit ToT counters and is stored in a centralized latency buffer for transmission to the End Of Column logic in the case of a matching trigger signal. A more detailed description of the CHIPIX65 digital functionality can be found in [9].…”

Section: Introductionmentioning

confidence: 99%

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First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

Panati

Paterno

Monteil

et al. 2016

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/R

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Section: B Region Digital Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

Panati

Paterno

Monteil

et al. 2016

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/R

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“…In particular, the DBA was implemented with a 2×2 pixel region configuration in the FE65-P2 prototype [13], featuring a buffer depth of 7 both in the local ToT memory and in the shared hit time memory. The CBA, instead, was implemented in the CHIPIX65 prototype [14] using 4×4 pixel regions. The write logic is such that the ToT is counted within a fixed dead time, which is equal to the time needed to compute the longest possible value; the end of the processing is flagged to a region digital writer module, which saves into the shared buffer a reduced information packet containing timestamp, a binary hit map of every pixel in the region, and up to six pixel ToTs.…”

Section: Rtl Studymentioning

confidence: 99%

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

et al. 2018

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The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted. K: Digital electronic circuits; Front-end electronics for detector readout; Pixelated detectors and associated VLSI electronics; Simulation methods and programs 1Corresponding author.

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“…The chip is composed of an array of 64 × 64 cells with 50 µm × 50 µm pixel size and integrates two different architectures of analog front-ends working in parallel, one synchronous [2] and one asynchronous [3]. An innovative region-based digital Centralized Buffering Architecture (CBA) grouping 4 × 4 pixels has been implemented in order to withstand 3 GHz/cm 2 hit rate and extended trigger latencies foreseen at HL-LHC [4]. A more exhaustive description of prototype implementation details can be found in [5].…”

Section: Introductionmentioning

confidence: 99%

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

Pacher¹,

Ratti²,

Licciulli³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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-A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 µm × 50 µm pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 µm × 50 µm and single readout electrode 25 µm × 100 µm 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre-and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology.

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New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for HEP detectors at HL-LHC

Cited by 5 publications

References 13 publications

First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

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