A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

Abstract

The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted. K: Digital electronic circuits; Front-end electronics for detector readout; Pixelated detectors and associated VLSI electronics; Simulation methods and programs 1Corresponding author.

Analog front-end characterization of the RD53A chip

“…It can be reduced by increasing the preamplifier discharge current, which makes the preamplifier discharge faster. Simulations show that in order to achieve the required 1 % dead time in the innermost layer, it is necessary to discharge an equivalent input charge of 3000 e − within one LHC clock cycle (25 ns) [6]. This corresponds to a typical signal of 6000 e − having a time-overthreshold (TOT) of two clock cycles.…”

Radiation-induced effects on data integrity and link stability of the RD53A pixel readout chip

“…A pixel core can be simulated on transistor-level. All pixel cores are identical, which allows for efficient hierarchical verification [8].…”