First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

Panati, Serena; Paterno, A.; Monteil, E.; Pacher, L.; Demaria, N.; Rivetti, A.; Rolo, M.; Wheadon, R.; Rotondo, F.; Dellacasa, G.; Licciulli, F.; Loddo, F.; Ciciriello, F.; Marzocca, C.; Mattiazzo, Serena; Canio, F. De; Gaioni, L.; Re, V.; Traversi, G.; Ratti, L.; Marconi, S.; Magazzù, G.; Stabile, A.; Placidi, P.

doi:10.1109/nssmic.2016.8069857

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…Off-line data analyses are then performed using a set of Python/ROOT macros. Extensive pre-irradiation electrical tests validated expected chip functionalities [6]. All global DACs and the monitoring ADC placed at the chip periphery exhibit excellent linearity in agreement with simulations, providing reliable bias conditions and charge-injection characteristic for analog front-ends characterizations.…”

Section: Summary Of Pre-irradiation and Post-irradiation Resultssupporting

confidence: 58%

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

Pacher¹,

Ratti²,

Licciulli³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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-A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 × 64 pixels with 50 µm × 50 µm pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 µm × 50 µm and single readout electrode 25 µm × 100 µm 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre-and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology.

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Section: Summary Of Pre-irradiation and Post-irradiation Resultssupporting

confidence: 58%

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

Pacher¹,

Ratti²,

Licciulli³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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“…A Phase-Locked Loop (PLL) device generates the high-speed clock required in the highspeed (dark blue) uplinks. Radiation tolerant Serializer (SER) and Deserializer (DES) allow the communication with more FE modules, as four RD53A front-ends [10], achieving a whole data rate up to 10 Gbps. While the electrical driver and receiver work as interfaces for the optical side (photodiode and MZM).…”

Section: Detector Modulementioning

confidence: 99%

A high-speed driver for silicon photonics Mach-Zehnder modulator for high data-rate transfer of particle collision images in high-energy physics and in medical physics

Saponara¹,

Magazzù

Ciarpi

2018

Real-Time Image and Video Processing 2018

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New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for HEP detectors at HL-LHC

Paterno

Pacher

Demaria

et al. 2016

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/R

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First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC

Cited by 4 publications

References 10 publications

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

A high-speed driver for silicon photonics Mach-Zehnder modulator for high data-rate transfer of particle collision images in high-energy physics and in medical physics

New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for HEP detectors at HL-LHC

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