Neural Network Implementation in Hardware Using FPGAs

Şahin, Sühap; Becerikli, Yaşar; Yazıcı, Süleyman

doi:10.1007/11893295_122

Cited by 69 publications

(46 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Intel and Xilinx produce FPGA that has the ability to reconfigure the hardware [49]. Identifying the purpose of reconfiguration highlights the motivation behind different implementation approaches [63].…”

Section: Fpgamentioning

confidence: 99%

“…A method of implementing a fully connected feed forward network with Xilinx FPGAs for image processing in a way that a single processing node is partitioned into two XC3090 chips is proposed in [63]. It explores the way to implement fully parallel ANN and efficiently use 32-bit floating-point numeric representation in FPGA-based ANNs by making use of the features of SpartanIIE series FPGAs.…”

Section: Fpgamentioning

confidence: 99%

See 1 more Smart Citation

Hardware Design for Machine Learning

Jawandhiya¹

2018

IJAIA

View full text Add to dashboard Cite

show abstract

Section: Fpgamentioning

confidence: 99%

Section: Fpgamentioning

confidence: 99%

Hardware Design for Machine Learning

Jawandhiya¹

2018

IJAIA

View full text Add to dashboard Cite

show abstract

“…In the proposed routing protocol, nodes need to only be aware about the locations of nearest neighbors" in the cluster; through the network the data packets are routed by being forwarded to a cluster. The major advantages of geographic routing over other routing strategies of WSNs include; (i) stateless, and therefore highly energy efficient, nature of routing, (ii) fast adaptability to network"s topological changes, and (iii) scalability [24][25] which should be the main objectives while deploying any type of WSN. These distinguished characteristics makes the protocol efficient, simple, and physically deployable, averting the use of practical routing that can originate complexity and also overhead in the mobile framework.…”

Section: The Proposed Frameworkmentioning

confidence: 99%

A Heterogeneous Framework to Detect Intruder Attacks in Wireless Sensor Networks

Al-Fayoumi¹,

Ahmad²,

Tariq³

2016

ijacsa

View full text Add to dashboard Cite

Abstract-Wireless sensor network (WSN) has been broadly implemented in real world applications, such as monitoring of forest fire, military targets detection, medical and/or science areas and above all in our daily home life as well. Nevertheless, WSNs are effortlessly compromised by adversaries due to their broadcast transmission medium as a means of communication which are lacking in tamper resistance. Consequently, an intruder can over hear all traffic, replay previous messages, inject malicious data packets, or can compromise a node. Commonly, sensor nodes are very much vulnerable of two main issues in security aspect that are node authentication and compromising a node. In this paper, a heterogeneous framework of node capture and intrusion detection for WSNs is proposed. This framework efficiently detects the captured nodes by using a novel technique, embedded with an Intrusion Detection mechanism which aggregates Signature and Anomaly based approach with Neural Network Multi-Layer Perceptron (MLP) classification in a clustering environment. Moreover, the proposed framework achieves efficiency at reasonable computation and communication costs and it can be a security shield to real WSN applications.

show abstract

“…Fully parallel feed-forward ANN architecture is illustrated to review the importance of datapath architectures. Figure 3 shows the 3 layered ANN where number of multipliers per neuron will be equal to number of connections to this neuron and the number of adders will be equal to number of connections to previous layer minus one [9].…”

Section: Multi-layer Ann Architectuementioning

confidence: 99%

Low Power Adder based ANN

Prasad¹,

Kulkarni²

2015

IJCA

View full text Add to dashboard Cite

This paper presents an overview of datapath realizations of the Hardware neural network models which perform massive parallel operations for best results and real time applications. Digital implemented neural models processing element -adder with low power consumption is proposed for real-time multimedia applications. Proposed adder is illustrated in the 2-3-1 tree layer artificial neural network (ANN). Designs were modeled with Verilog HDL and implemented in FPGA domain by targeting the Virtex 7 device.

show abstract

Neural Network Implementation in Hardware Using FPGAs

Cited by 69 publications

References 7 publications

Hardware Design for Machine Learning

Hardware Design for Machine Learning

A Heterogeneous Framework to Detect Intruder Attacks in Wireless Sensor Networks

Low Power Adder based ANN

Contact Info

Product

Resources

About