Networks on silicon: combining best-effort and guaranteed services

Goossens, Kees; Meerbergen, J. van; Peeters, A.; Wielage, R.

doi:10.1109/date.2002.998309

Cited by 81 publications

(57 citation statements)

References 5 publications

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“…Furthermore, the ability of an NoC to provide guaranteed services enables a designer to make critical timing decisions early in the design process, thus avoiding unnecessary design iterations [33].…”

Section: Qos For Nocsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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Section: Qos For Nocsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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“…NoC can also improve design productivity by supporting modularity and reuse of complex cores, thus enabling a higher level of abstraction in architectural modeling of future systems [4], [5]. However, VLSI designers must be ensured that the benefits of NoC do not compromise system performance and cost [8], [10]. Performance concerns are associated with latency and throughput.…”

Section: Abstract-we Define Quality Of Service (Qos) and Cost Model Fmentioning

confidence: 99%

“…As described in [1], [9], memory and computing resources are relatively more expensive on-chip, while relatively more wires are available. The need to combine several types of service, such as "best effort" and "guaranteed throughput" was noted by [1], [8]. In [9] it was suggested to support several access paradigms such as request-response (for compatibility with bus-based approaches) and connection-oriented services for extended functionality.…”

mentioning

confidence: 99%

“…From several aspects they can be considered as networks but still, they don't provide effective spatial reuse of resources and do not utilize packet or wormhole switching associated with distributed routing and congestion/flow control. Therefore, they are inefficient and require centralized arbitration mechanisms.Advantages of spatial-reuse packet/wormhole switched networks were analyzed in comparison with buses by several authors [1], [3], [5], [8], [9]. A hybrid approach, supporting both NoC and on-chip buses has been proposed in [10].…”

mentioning

confidence: 99%

“…Advantages of spatial-reuse packet/wormhole switched networks were analyzed in comparison with buses by several authors [1], [3], [5], [8], [9]. A hybrid approach, supporting both NoC and on-chip buses has been proposed in [10].…”

mentioning

confidence: 99%

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