"NET-AN" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications

Akcasu, O.E.; Lu, Jianping; Dalal, Ankit; Mitra, S.; Lev, L.; Vassegihi, N.; Pance, A.; Hingarh, H.; Basit, H.

doi:10.1109/iedm.1995.499246

Cited by 12 publications

(5 citation statements)

References 4 publications

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“…We assume that these elements belong to conductors. The matrix with size can be transferred into matrix with size , which is satisfied by the following: (11) After the condensing, a smaller matrix is obtained. Such a matrix is exactly the BCM of the domain with a single dielectric.…”

Section: ) Bcm Of the 3-d Domain With Single Dielectricmentioning

confidence: 99%

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

Wang

2004

IEEE Trans. Microwave Theory Techn.

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Abstract-As feature size decrease, fast and accurate parasitic capacitance extraction has become increasingly critical for verification and analysis in very large scale integration design. In this paper, a fast hierarchical-block boundary-element method based on the boundary-element method (BEM) is presented for threedimensional (3-D) capacitance extraction, which can give out the global capacitance matrix directly. It assigns the global computation of 3-D domain into local computation in BEM blocks by hierarchical partition 3-D structure. The boundary capacitance matrix (BCM) is computed in the BEM block using all the known conditions. Reuse technology can decrease the running time. After merging the BCMs of all BEM blocks, the global capacitance matrix for a given set of conductors can be computed. Numerical results show that this global hierarchical approach can get very high speed in 3-D computation with equal accuracy as the 3-D field solver.Index Terms-Boundary-element method (BEM), capacitance extraction, hierarchical, very large scale integration (VLSI).

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Section: ) Bcm Of the 3-d Domain With Single Dielectricmentioning

confidence: 99%

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

Wang

2004

IEEE Trans. Microwave Theory Techn.

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“…It was also determined that the additional via resistance that are associated with the TDL structure do not significantly influence the results. Finally, the noise performance of the TDL structure was simulated using the full 3-D extraction/simulation package OEA-NETAN [8], which confirms the theoretical model expectations and the simulations made using the PEEC-based model (Figure 7). …”

Section: Simulation Resultsmentioning

confidence: 51%

“…It is assumed that the line pair is periodically twisted at an interval length of 10µm. The twisted line segments were modeled using the full PEEC model (as shown in Figure 1), including partial resistance, capacitance, inductance as well as coupling capacitance and mutual inductance values calculated by the 3-D extraction package OEA-NETAN (METAL/HENRY) ® [8]. In all simulations, the aggressor is driven by a signal with rise/fall time of 100ps, while the victim line input is kept at a constant DC level (not left floating).…”

Section: Simulation Resultsmentioning

confidence: 99%

Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation

Hatirnaz

Leblebici

Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)

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A simple generic interconnect architecture is presented to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines. The approach is based on the principle of constructing periodically twisted differential line pairs for parallel interconnect segments in order to eliminate the mutual coupling influences. Detailed 3-D simulations show that a crosstalk noise reduction of up to 60 dB is achievable with this approach.

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“…The line segments were modeled using the full PEEC model (as shown in Figure 1), including partial resistance, capacitance, inductance as well as coupling capacitance and mutual inductance values calculated by the 3-D extraction package OEA-NETAN (METAL/HENRY) ® [7]. Figure 4 shows the change in wire delay versus wire length for single-straight lines and differential lines.…”

Section: Simulation Resultsmentioning

confidence: 99%

Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction

Hatirnaz

Leblebici

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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A simple generic interconnect architecture is presented to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines. The approach is based on the principle of constructing periodically twisted differential line pairs for parallel interconnect segments in order to eliminate the mutual coupling influences. Detailed simulations show that the twisted-differential lines (TDL) provide high-speed and crosstalk-immnune interconnects, compared to single-ended and differential lines.

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"NET-AN" a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications

Cited by 12 publications

References 4 publications

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation

Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction

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