Abstract-As feature size decrease, fast and accurate parasitic capacitance extraction has become increasingly critical for verification and analysis in very large scale integration design. In this paper, a fast hierarchical-block boundary-element method based on the boundary-element method (BEM) is presented for threedimensional (3-D) capacitance extraction, which can give out the global capacitance matrix directly. It assigns the global computation of 3-D domain into local computation in BEM blocks by hierarchical partition 3-D structure. The boundary capacitance matrix (BCM) is computed in the BEM block using all the known conditions. Reuse technology can decrease the running time. After merging the BCMs of all BEM blocks, the global capacitance matrix for a given set of conductors can be computed. Numerical results show that this global hierarchical approach can get very high speed in 3-D computation with equal accuracy as the 3-D field solver.Index Terms-Boundary-element method (BEM), capacitance extraction, hierarchical, very large scale integration (VLSI).
-Several techniques are presented for the efficient resistance calculation of wiring structures in flat panel display (FPD). The techniques are based on two-dimensional boundary element method (BEM), suitable for the geometry characteristics of the FPD structures. With an automatic strategy for boundary element partition and the analytical BEM-coupled approach, the proposed resistance solver shows good accuracy and fast computational speed. Numerical experiments demonstrate that the solver can be more than 10,000 times faster than the finite difference solver RAPHAEL while preserving good accuracy. And the proposed techniques accelerate the original BEM remarkably. Structures from real FPD designs have validated the efficiency of the proposed techniques.
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