Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)
DOI: 10.1109/issoc.2003.1267725
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Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation

Abstract: A simple generic interconnect architecture is presented to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines. The approach is based on the principle of constructing periodically twisted differential line pairs for parallel interconnect segments in order to eliminate the mutual coupling influences. Detailed 3-D simulations show that a crosstalk noise reduction of up to 60 dB is achievable with this approach.

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Cited by 10 publications
(3 citation statements)
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References 6 publications
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“…Thanks to its differential nature, MCML offers considerable potential for improving the signal integrity in digital logic circuits [2]. Other advantages of MCML logic style include a reduced power consumption at very high-speed [1] and improved security in cryptography applications [3].…”
Section: Introductionmentioning
confidence: 99%
“…Thanks to its differential nature, MCML offers considerable potential for improving the signal integrity in digital logic circuits [2]. Other advantages of MCML logic style include a reduced power consumption at very high-speed [1] and improved security in cryptography applications [3].…”
Section: Introductionmentioning
confidence: 99%
“…1) Differential design: As highlighted in section III-A, an essential design technique to improve the isolation is the use of a differential architecture. A fully differential circuit design approach allows rejecting common-mode effects such as supply and substrate noise [11].…”
Section: Isolation Techniquesmentioning
confidence: 99%
“…To allow a perfect cancellation of coupled magnetic and electric field components between two parallel adjacent lines, we consider using twisted differential line (TDL) [4].…”
Section: Inductive Coupling Basicsmentioning
confidence: 99%