NBTI modeling in analog circuits and its application to long-term aging simulations

Giering, Kay-Uwe; Sohrmann, Christoph; Rzepa, G.; Heis, Leonhard; Jancke, Roland

doi:10.1109/iirw.2014.7049501

Cited by 15 publications

(5 citation statements)

References 16 publications

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“…A framework in the simulator must be included which can cover hot carrier degradation (HCD), both positive and negative bias temperature instability (P/NBTI), TDDB and Electro-migration (EM), etc. [201][202][203]. The exact information of all these models is needed to accurately predict the reliability either at the device level or circuit level.…”

Section: (I)mentioning

confidence: 99%

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NVmemory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

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Section: (I)mentioning

confidence: 99%

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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“…Our fast solution algorithm [10] to the above ODE rewrites 𝑤(𝑡) using matrix notation. We calculate the time integrals…”

Section: Compact Modelmentioning

confidence: 99%

“…For the case of periodic digital stress, the closed-form solution to this differential equation is known [4]. This solution was generalized to periodic analog stress voltages in [10]; a related approach was given in [11]. The parametrization [12] of the gate-source voltage (𝑉 gs ) dependence of CET maps can be an input to future analog-stress NBTI models.…”

Section: Introductionmentioning

confidence: 99%

Analog-circuit NBTI degradation and time-dependent NBTI variability: An efficient physics-based compact model

Giering

Rott

Rzepa³

et al. 2016

2016 IEEE International Reliability Physics Symposium (IRPS)

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We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages and thus go beyond existing NBTI studies for digital stress. As a result, we propose a physics-based compact model for analogstress NBTI which builds upon the extensive TCAD analysis of our ultra-short-delay experimental data. The numerical efficiency of the compact model allows its direct coupling to electric circuit simulators and permits to accurately account for NBTI degradation already during circuit design. Our model enables the calculation of the time-dependent NBTI variability of single device and of circuit performance parameters. We demonstrate our NBTI model on an operational amplifier and calculate the mean drift and variability of its offset voltage

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“…) inherit (from the analog gate-source voltage V gs ) the property of taking continuous values. A fast solution algorithm [7] rewrites w(t) as follows: the quantities…”

Section: Bti Compact Modelmentioning

confidence: 99%

“…Advanced digital-stress modelings introduce capture-emission time (CET) maps and calculate the mean degradation mostly analytically [6]. Their generalization to analog stress [7,8] takes into account the defect dynamics beyond CET maps. Deeply scaled technologies show a strong NBTI variability, the corresponding statistical distributions [9,10] were applied to an SRAM failure analysis under timeindependent BTI stress [11] with high resolution of the distribution tails.…”

Section: Introductionmentioning

confidence: 99%

BTI variability of SRAM cells under periodically changing stress profiles

Giering

Lange

Kaczer

et al. 2016

2016 IEEE International Integrated Reliability Workshop (IIRW)

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We present a BTI compact model that is able to account for the complex BTI stress patterns encountered in complex electronic circuits. Such stress patterns are composed of various blocks corresponding to different circuit operation states, protocol modes or input conditions, and the blocks repeat within a composite, hierarchical structure. The present work extends a previously introduced physics-based accurate NBTI modeling while preserving its numerical efficiency. We provide insight into some principal characteristics of BTI degradation under hierarchical stress patterns, such as a non-trivial dependence on multiple duty cycles. In particular, the NBTI degradation can sensitively depend on the temporal sequence of NBTI stress blocks, and building a model on just the average stress or on stress histograms can be misleading. An SRAM cell example demonstrates this method and compares the cell's BTI failure statistics for two different hierarchic-periods stress patterns

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NBTI modeling in analog circuits and its application to long-term aging simulations

Cited by 15 publications

References 16 publications

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

Analog-circuit NBTI degradation and time-dependent NBTI variability: An efficient physics-based compact model

BTI variability of SRAM cells under periodically changing stress profiles

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