The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.

Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NVmemory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C 2 MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C 2 MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C 2 MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

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We have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.

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This work aimed at developing a full adder using hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) based on the logic-in-memory architecture (LIM). LIM has emerged as the most promising alternative to the standard von-Neumann architecture in the impeding post-CMOS era. Performance of the hybrid full adder is evaluated in terms of power, delay, power delay product (PDP), and device count. These results are compared with the existing double pass transistor logic-based clocked CMOS (DPTL-C2MOS) full adder. Further, Monte-Carlo simulations on both variants of full adders were conducted to study their performance. Simulation results reveal that the hybrid full adder is superior to the DPTL-C2MOS full adder and can be used in low power and high throughput computing systems in the near future.