NBTI-aware synthesis of digital circuits

Kumar, Sanjay; Kim, Chris H.; Sapatnekar, Sachin S.

doi:10.1145/1278480.1278574

Cited by 99 publications

(76 citation statements)

References 8 publications

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“…5, where the delays at different time stamps are plotted. The transient performance of the circuit is compared with the case where the worst-case synthesis based approach from [6]. Worst case BTI-based library gate delays were used during technology mapping to synthesize the circuit, to meet the same spec.…”

Section: A Comparison Of Transient Power and Delay Numbersmentioning

confidence: 99%

“…Previous approaches to guard-banding a circuit and ensuring optimal performance over its lifetime, such as sizing [4], [5], and synthesis [6] can be classified as "one-time" solutions that add appropriate guard-bands at design time. These methods are generally formulated as optimization problems of the type:…”

Section: Introductionmentioning

confidence: 99%

“…The work in [6] argues that synthesis can lead to area and power savings, as compared with sizing optimizations, thereby resulting in a lower amount of guard-band. However, guard-banding (through sizing or synthesis) is performed during design time, and is a one-time fixed amount of padding added into the circuit in the form of gates with a higher drive strength.…”

Section: Introductionmentioning

confidence: 99%

“…Both the sizing [5] and synthesis [6] approaches have shown reductions in the area and power overhead in using a signal probability profile to determine the delay of the circuit, inside the optimization engine, as opposed to computing the worst-case delay degradation of the circuit, based on [4]. However, it is not possible to compute the asymptotic signal probabilities, over the entire lifetime operation of the circuit, in an accurate manner.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guardbands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.

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Section: A Comparison Of Transient Power and Delay Numbersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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“…Based on these NBTI-aware circuit performance degradation models and STA techniques, researchers have investigated design techniques that can mitigate NBTI effects, such as transistor sizing [13], adjustment of dynamic operation conditions (supply voltage (V dd ), temperature (T ), and signal probability (SP)) [11], bit-flipping technique [14]. Higher level technique, such as NBTI-aware synthesis [15] was also studied.…”

Section: Introductionmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

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Power-Gating for Leakage Control and Beyond

Calimera¹,

Macii²,

Macii³

et al. 2014

Circuit Design for Reliability

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The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supplyvoltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware PowerGating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5 in the presence of NBTI.

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NBTI-aware synthesis of digital circuits

Cited by 99 publications

References 8 publications

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Power-Gating for Leakage Control and Beyond

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