Power-Gating for Leakage Control and Beyond

Abstract

The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supplyvoltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware PowerGating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5 in the presence of NBTI.

Implications of accelerated self-healing as a key design knob for cross-layer resilience

“…1) Active Recovery by Negative Voltage: In modern chips, when certain blocks go to sleep, the supply voltage is usually gated to reduce leakage, and this also helps the recovery of wearout such as BTI, but this only results in passive recovery [43]. For the proposed active recovery (refer to Fig.…”

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

“…Thus, this paper explores one more circuit-level technique, called sleep transistor, for increasing the robustness of a set of FinFET logic gates under these challenges. This approach already was studied in [13] for process variability mitigation in planar technologies. The technical drawbacks about area, performance and power consumption are briefly reported in this work.…”

“…The power-gating is one strategy widely employed in low power designs to shut off the circuit blocks that are not in use, improving the overall power on a chip [13]. The difference among the power-gating designs is the granularity of the blocks.…”

“…This work focuses on a fine-grained model where a sleep transistor is added to every FinFET cell. However, for larger circuits, the block-grained style is more indicated to avoid the area overhead [13]. Fig.…”

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

“…The target of this work is to bring the Vdd-Hopping concept at a lower level of granularity, i.e., within the core. The basic concept behind this idea is not new as it follows the natural scaling other power-management strategies experienced in the last years, e.g., Multi-Vdd, Body-Biasing, Power-Gating [11][12][13]. The taxonomy tree shown in Fig.…”