Nanotube Junctionless FET: Proposal, Design, and Investigation

Sahay, Shubham; Kumar, M. Jagadesh

doi:10.1109/ted.2017.2672203

Cited by 113 publications

(35 citation statements)

References 32 publications

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“…We also studied the behaviour of GC‐EDD‐JAMFET and observed further enhancement in device characteristics. We believe that the use of proposed technique can also be integrated in emerging nanowire devices with lesser process complexity than nanotube structures proposed by Tekleab [27] and Sahay and Kumar [28]. Thus, the proposed EDD‐JAMFET can be an appropriate alternative at scaled technology nodes.…”

Section: Resultsmentioning

confidence: 90%

Design approach to improve the performance of JAMFETs

Raushan

Alam

Siddiqui

2020

IET Circuits, Devices & Systems

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In this paper, the authors propose the use of electrostatic doping for n + drain region formation in Junctionless accumulation mode field effect transistors (JAMFET). This electrostatically doped drain (EDD) JAMFET employs an additional unbiased electrode (auxiliary electrode) of low workfunction on the intrinsic drain region. This technique effectively suppresses the tunneling leakage, thereby reducing I OFF by 6 orders. The tunneling of electrons from valence band of channel to conduction band of drain happens due to enhanced band bending in OFF-state (V GS = 0 V, V DS = 1 V). The presence of additional electrode in EDD-JAMFET increases the width of tunnel barrier formed at channel-drain junction in OFF-state improving the I ON /I OFF ratio by 6 orders. The gate length scaling demonstrates that leakage suppression of EDD-JAMFET is more effective with approximately 3 orders smaller I OFF even at gate length of 5 nm. The performance of graded channel device (GC-EDD-JAMFET) by electrostatic doping is also explored. Significant improvements are observed in terms of I ON /I OFF , subthreshold slope SS, DIBL and f T. Finally, the analogue parameters such as Transconductance generation factor G m /I D , Intrinsic gain A V , output conductance G D , and 'G m /I D × f T ' performance metrics are investigated which show significant improvement at small bias current, making it suitable for ultra-low power applications.

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Section: Resultsmentioning

confidence: 90%

Design approach to improve the performance of JAMFETs

Raushan

Alam

Siddiqui

2020

IET Circuits, Devices & Systems

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“…In GAA‐SNWTs, the current carrying capacity is proportional to the channel perimeter of device, so by dividing the current carrying capacity with the effective silicon film circumference (i.e.

π \times d_{NW}

), the drain current is normalised [23]. To achieve high gain in sub‐threshold to weak inversion region, the device analogue/Rf performance is elicited at

10 μ m / μ A

drain current [24].…”

Section: Device Structure and Propertiesmentioning

confidence: 99%

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective

Gupta

Nandi

2019

IET Circuits, Devices & Systems

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Here, a comprehensive study of the gate-all-around silicon nanowire field effect transistor (FET) (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of air as spacer dielectric, on analogue/RF behaviour of the device. Parasitic capacitances in nanoscale devices contribute a dominating role in overall device capacitances. Introducing air as spacer dielectric (ε SP) in source/drain underlap region, device parasitic capacitances deteriorates, which improves the overall capacitances. Thus, the analogue/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low-power high-frequency operations. For targeting low power applications, FOMs are elicited at 10 μA/ μm. It is perceived that intrinsic gain of the device is almost unaltered for distinct spacer dielectric (Si 3 N 4 and air). Frequencies like cutoff frequency (f T) and maximum oscillation frequency (f MAX) of air spacer dielectric-based underlap GAA-SNWTs are enhanced by 2.92 times and 3.11 times, respectively, when contrasted by the Si 3 N 4 spacer-based GAA-SNWTs. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).

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“…To make the device JL the same doping concentration is used in the source, channel, and drain regions also. SiO 2 is used for the gate dielectric as well as for the side wall spacer [16].…”

Section: Device and Simulation Characterisationmentioning

confidence: 99%

“…The metal gate work function of N‐JLSiNT FET is set at 4.8 eV whereas the metal gate work function of P‐JLSiNT FET is tuned to match the off‐current ( I off ) with N‐JLSiNT FET. The effective channel width ( W ) is π ( d + T Si ), where d is the diameter of inner gate [16]. The inner and outer gates of the nanotube (NT) are simultaneously driven by a common gate voltage ( V gs ).…”

Section: Device and Simulation Characterisationmentioning

confidence: 99%

“…Subsequently, JL SiNT FET is first investigated by Ambika and Srinivasan [15]. Sahay and Kumar [16] show that JLSiNT FET offers better on‐current to off‐current ratio ( I on / I off ) and the sub‐threshold slope (SS) as compared to JLSiNW FET. Furthermore, to reduce the total gate capacitance ( C gg ) associated with JLSiNT FET, we have proposed the concept of underlap inner gate in JLSiNT FET in our earlier work [17].…”

Section: Introductionmentioning

confidence: 99%

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Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

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This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on /C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on /I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

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Nanotube Junctionless FET: Proposal, Design, and Investigation

Cited by 113 publications

References 32 publications

Design approach to improve the performance of JAMFETs

Design approach to improve the performance of JAMFETs

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

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