Multiplication Acceleration Through Twin Precision

Själander, Magnus; Larsson-Edefors, Per

doi:10.1109/tvlsi.2008.2002107

Cited by 34 publications

(39 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Their modifications have given a significant improvement in realizing a multiplier with less area, delay, and power [4,5]. Magnus Sjalander and Per Larsson-Edefors [6] have presented a twin precision algorithm to accelerate multiplication. The implemented multiplier has low power dissipation and enables an increased computational throughput.…”

Section: Introductionmentioning

confidence: 99%

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Abbasi

Zulhelmi

Alamoud

2015

IEICE Electron. Express

View full text Add to dashboard Cite

This research is about a new approach, which is used for optimizing multipliers designs, which are based on the concept of Vedic mathematics. The design has been targeted to to FPGAs (state-of-the art field-programmable gate arrays). It has been assessed that the multiplier produces partial products by utilizing Vedic mathematics concept by deploying basic 4 × 4 multipliers, which is designed by exploiting special features of multiplexers and 6-input look up tables (LUTs) on the same slices, resulting in considerable minimization in area. The multiplier has been realized on Xilinx® Virtex-5 FPGAs. It is significant to notice that pipeline adders were used to obtain final products. Furthermore, the multiplier is developed and organized by using pipeline schemes, which contribute to the enhancement of operating frequency of the multiplier. The results show that the 32-bit pipeline multiplier can work up to a clock frequency of 450 MHz. It has utilized 514 slices and 1157 flip-flops and has much less dynamic power than the other reported work.

show abstract

Section: Introductionmentioning

confidence: 99%

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Abbasi

Zulhelmi

Alamoud

2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In this paper, we narrowed our research work towards achieving double throughput in signed multipliers with lesser hardware complexity. Twin precision (TP) is the technique that can be exploited to obtain the dual output [1] in multipliers, and this technique was implemented for both signed and unsigned multipliers [2].…”

Section: Introductionmentioning

confidence: 99%

“…In [2], double throughput is realised effectively by adopting TP technique in MB multiplier. MB algorithm [10] is a widely used signed algorithm since it has reduced partial product row.…”

Section: Introductionmentioning

confidence: 99%

“…While implementing TP technique in the signed multipliers like MB [2], multiplexers are involved for the selection of partial products during N and N/2 b multiplication. This addition of multiplexers give rise to an area overhead, and thereby significant delay is added in the TP multiplier.…”

Section: Introductionmentioning

confidence: 99%

“…This addition of multiplexers give rise to an area overhead, and thereby significant delay is added in the TP multiplier. By making the calculation of multiplexer utilisation, the TP implementation in MB multiplier [2] utilises N + 3 multiplexers to select the partial products. The unwanted partial products that are not in use for N/2 bit multiplication are set to zero by modifying two input AND gate which produces partial products to three input AND gate and the third input is the control signal.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An optimised twin precision multiplier for ASIC environment

Asirvatham¹,

Ramachandran²

2015

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

In this paper, we present the performance of twin precision technique in reduced computation modified booth (RCMB) multiplier to achieve double throughput, and an algorithm is proposed. Twin precision technique is the efficient way to obtain double throughput in the multipliers. We describe how to apply twin precision technique to RCMB multipliers. Implementation of twin precision in RCMB multiplier requires lesser changes to be made in partial product array for obtaining double throughput. Multiplexers usually do the signal selection for N and N/2 bit multiplication. In RCMB multiplier, [N/2] + 1 partial product are reduced to N/2 rows. Our idea of implementing twin precision technique to RCMB results in less utilisation of multiplexers of about [N/2] + 3 which gave a way for optimization in the twin precision (TP) multiplier. Thereby, we have achieved the drastic reduction in multiplexer utilisation of about 40% to 50% (for N = 8 to 128) compared to the existing twin precision modified booth multiplier. In our proposed optimised TP modified booth multiplier this reduction in multiplexers gave a way for overall reduction in area, power and delay. Lesser utilisation of multiplexer results in the area reduction of about 5% to 18%, delay of 5% to 20% and a considerable reduction in power of 8% to 32% were noticed in the proposed TP booth multiplier for N = 8 to 128. Our proposed optimised TP multiplier is implemented in FFT complex multiplication which is taken as an application case study and achieves better performance (area, delay and power) compare to prior TP multiplier. All our evaluation are made using cadence RTL compiler using TSMC 180 nm library.

show abstract

Memory Based Multiplier Design in Custom and FPGA Implementation

Basiri

Mahammad

2015

Advances in Intelligent Systems and Computing

View full text Add to dashboard Cite

Multiplication Acceleration Through Twin Precision

Cited by 34 publications

References 28 publications

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

An optimised twin precision multiplier for ASIC environment

Memory Based Multiplier Design in Custom and FPGA Implementation

Contact Info

Product

Resources

About