FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Abbasi, Shuja A.; Zulhelmi,; Alamoud, A.R.M.

doi:10.1587/elex.12.20150450

Cited by 5 publications

(4 citation statements)

References 12 publications

(24 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, in a binary subtraction, the rst number must be added to the second number's two's complement using Sankalana after rst adding the second number's one to its two's complement using Purak and Ekadhika whereas multiplication is carried using [13] "Urudhva Triyagbyham"and "Dhwajam" Algorithm if using Vedic sutra. Urudhva Triyagbyham sutra Algorithm used for implementing Multiplication: Urudhva [14] means "Vertically up and down" .Triyagbyham means "left or right" or vice versa.…”

Section: Proposed Methodsmentioning

confidence: 99%

Design of High Speed Arithmetic Processor Using Vedic Mathematics

ShanmugaSundaram

2022

Preprint

View full text Add to dashboard Cite

Digital Computer Arithmetic is an aspect of logic design with the objective of developing algorithms in order to achieve effective utilisation of available hardware and resources. The Arithmetic and Logical Unit is the critical component of a microprocessor and a central processing Unit. ALU comprises of combinational and Arithmetic units that perform operations like AND, OR, NOR etc. and Addition, subtraction, multiplication respectively. Hence an algorithm with ultimate speed and minimum chip area are the most often used measures to determine the Efficiency of an algorithm. This Paper presents a fast scheme for arithmetic computations with reduced Area in order to achieve High Speed. Since there is a strong link between Algorithm and the technology used for its Implementation, Vedic sutras implementation in an FPGA environment due to its ease of Application is discussed here .This Paper addresses the design of High speed Architecture for Addition, Subtraction, Multiplication, Division operations using Vedic maths. The proposed Vedic Maths Sutras (computation protocol) that are discussed in the present work exhibits its efficiency in terms of speed and area utilisation, as validated on FPGA.

show abstract

Section: Proposed Methodsmentioning

confidence: 99%

Design of High Speed Arithmetic Processor Using Vedic Mathematics

ShanmugaSundaram

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Multipliers with large width are required for the implementation of cryptography and error correction circuits for more reliable transmission over highly insecure and/or noisy channels in networking and multimedia applications. The hierarchical principle helps to realize fast large bit multiplier, except that it requires a large width adder for performing the addition task, which poses limitation on the performance and increases area of the designed multiplier [16][17][18].…”

Section: Hierarchy Multipliermentioning

confidence: 99%

“…However, this method requires twice the number of adders thus results in increased area. On the other hand, the delay is reduced with the deployment of carry look ahead adder for the addition process but this increases the interconnection complexity [17]. Not only delay and area, the power consumption of the hierarchy multiplier also has to be reduced because the existing designs appending more zeros to equalize the number of bits in order to make them suitable for parallel computation [18].…”

Section: Hierarchy Multipliermentioning

confidence: 99%

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

Mohan¹,

Nakkeeran²

2017

ELS

View full text Add to dashboard Cite

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and im age processing.

show abstract

“…Vedic Multiplier in [13] is based on basic 4-bit multiplier which has a fine regularity, but less efficient in implementing compressor array. Array Multiplier has a fine regularity in compressor array, and good efficiency in compression, but has too many partial products.…”

Section: Pipelined Multiplier Supporting Multi-operand Additionmentioning

confidence: 99%

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Wang

Lai

2016

IEICE Electron. Express

View full text Add to dashboard Cite

Embedded hard DSP block effectively improves FPGA performance for arithmetic circuits. This paper proposes a novel DSP architecture. By adopting a new Compressor Array, the proposed DSP can additionally supports multi-operand addition which current commercial devices do not support. This makes the DSP block more versatile to cover a wider range of applications. But supporting multi-operand addition will significantly increase routing congestion. To alleviate timing degeneration caused by the more congestion routing, we implement a pipelined design in the Compressor Array. The proposed DSP block is fabricated in 1P10M 65 nm bulk CMOS process, Test results show a 53.7% reduction in critical path delay compared to the Field Programmable Compressor Tree (FPCT).

show abstract

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Cited by 5 publications

References 12 publications

Design of High Speed Arithmetic Processor Using Vedic Mathematics

Design of High Speed Arithmetic Processor Using Vedic Mathematics

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Contact Info

Product

Resources

About