Design of High Speed Arithmetic Processor Using Vedic Mathematics

Abstract

Digital Computer Arithmetic is an aspect of logic design with the objective of developing algorithms in order to achieve effective utilisation of available hardware and resources. The Arithmetic and Logical Unit is the critical component of a microprocessor and a central processing Unit. ALU comprises of combinational and Arithmetic units that perform operations like AND, OR, NOR etc. and Addition, subtraction, multiplication respectively. Hence an algorithm with ultimate speed and minimum chip area are the most often used measures to determine the Efficiency of an algorithm. This Paper presents a fast scheme for arithmetic computations with reduced Area in order to achieve High Speed. Since there is a strong link between Algorithm and the technology used for its Implementation, Vedic sutras implementation in an FPGA environment due to its ease of Application is discussed here .This Paper addresses the design of High speed Architecture for Addition, Subtraction, Multiplication, Division operations using Vedic maths. The proposed Vedic Maths Sutras (computation protocol) that are discussed in the present work exhibits its efficiency in terms of speed and area utilisation, as validated on FPGA.