Memory Based Multiplier Design in Custom and FPGA Implementation

Basiri, M. Mohamed Asan; Mahammad, S. K. Noor

doi:10.1007/978-3-319-11218-3_24

Cited by 5 publications

(2 citation statements)

References 13 publications

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“…The Computational Memory Architecture (CMA) in [1]- [4] is based on a Compute-Line (CL) with built-in computing capabilities that shares many objectives with Near Data Processing (NDP) including Computing with Memory [5], [6] as in FPGAs, Computing in caches [7] using Computational RAM (CRAM) [8], [9], Near-Memory Processing [10], [11] and Processing In Memory (PIM) [11], [12]. In contrary, CL does not require dedicated computational, pre-charging and/or sensing circuitry logics to conduct a logical operation on locally stored data without any memory copy.…”

Section: Introductionmentioning

confidence: 99%

A Compute-line based Computational Memory Architecture using bit-line Keepers: Internals and Analysis

Azougagh¹

2020

IJATCSE

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The growth of Big Data, memory wall and power wall are posing unprecedented demand for Processing In Memory (PIM). A computational memory architecture supporting in bit-Line processing can be a major key for PIM to eliminate the overhead of moving data from processing unit to memory and vice versa. It promises high bandwidth, massive parallelism, and high energy efficiency. The existing PIM approaches concentrates mostly on near-memory processing (NMP) and/or in-memory processing (IMP). The Compute-line based Computational Memory Architecture (CCMA), or simply (multiple) compute-lines (CLs), represents a different way of approaching in-memory processing (IMP). A compute-line represents a line that carries fine-grained operations using connected memory cells. CL is based on (a selection of) a bit-line for processing elementary logical operations and a bit-line Keeper (KEEPER) for enforcing and stabilizing the outcome results. CCMA is backward compatible with the conventional Static Random Access Memory (SRAM) and can be used for state storing. In contrary to the conventional SRAM, it eliminates the need to pre-charge and sensing bit-line(s) for read and write operations which reduces bit-line activities and support in-place combinational logic which reduces data transfer latency. It introduces a considerable potential to reduce bandwidth and energy consumption by eliminating overhead of data movement when used as an in-memory computing. Moreover, it can easily support any specific interconnect topology between multiple compute-lines for parallel applications by hard wiring their input/output interfaces during chip fabrication. The CCMA designs the KEEPER circuitry so that, in one (or two) clock cycle(s) and through bit-line selection, its can multi-row read bit information from participating memory cells, bitwise logic compute selected operation and multi-row write to targeted memory cells. In this work, toward deep investigation of the CCMA architectures and perspective remarks, CL's capabilities and statistical analysis of running in-place logic operations are presented and showed potential computational and global energy savings.

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Section: Introductionmentioning

confidence: 99%

A Compute-line based Computational Memory Architecture using bit-line Keepers: Internals and Analysis

Azougagh¹

2020

IJATCSE

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“…For example, the

n \times n

bits multiplier can be used to perform one

n \times n

bits multiplication or two

false(n / 2 false) \times false(n / 2 false)

bits multiplications in parallel, which is explained as twin precision multiplier [10]. The quarter precision multiplier is proposed in [11], where Wallace tree [12, 13] multiplier is used to perform one

n \times n

bit multiplication or four

false(n / 2 false) \times false(n / 2 false)

bits multiplications in parallel. Similarly, double throughput MAC design using Baugh Wooley array multiplier is proposed in [14], where the

n \times n

bits MAC is used to perform one

n \times n

bits MAC or two

false(n / 2 false) \times false(n / 2 false)

bits MACs in parallel.…”

Section: Introductionmentioning

confidence: 99%

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Basiri

Mohammad

2017

IET Computers & Digital Techniques

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This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.

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Guarded Low Power Hardware Implementations

Bhargav,

Mohamed Asan Basiri

2023

2023 IEEE 7th Conference on Information and Communication Technology (CICT)

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Memory Based Multiplier Design in Custom and FPGA Implementation

Cited by 5 publications

References 13 publications

A Compute-line based Computational Memory Architecture using bit-line Keepers: Internals and Analysis

A Compute-line based Computational Memory Architecture using bit-line Keepers: Internals and Analysis

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Guarded Low Power Hardware Implementations

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