Multiple-valued minimization to optimize PLAs with output EXOR gates

Debnath, Debatosh; Sasao, Tsutomu

doi:10.1109/ismvl.1999.779702

Cited by 23 publications

(9 citation statements)

References 9 publications

(19 reference statements)

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“…If k > 0, derive the restriction f k of f and the corresponding reduction equations. Second, minimize f k with any standard method: two level logic as SOP [34], Reed Muller [42]; three-level logic as SPP [8,31,38] (OR of ANDs of EXORs), EXSOP [35,36] (EXOR of ORs of ANDs), or switching lattices, as proposed in this paper. We note that, in the worst case, the lattice minimization requires time exponential in the number of points of the function, however, this number is strongly reduced for f k if compared to f .…”

Section: Introductionmentioning

confidence: 99%

Composition of switching lattices for regular and for decomposed functions

Bernasconi

Ciriani

Frontini

et al. 2018

Microprocessors and Microsystems

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Multi-terminal switching lattices are typically exploited for modeling switching nano-crossbar arrays that lead to the design and construction of emerging nanocomputers. Typically, the circuit is represented on a single lattice composed by fourterminal switches. In this paper, we propose a two-layer model in order to further minimize the area of regular functions, such as autosymmetric and D-reducible functions, and of decomposed functions. In particular, we propose a switching lattice optimization method for a special class of "regular" Boolean functions, called autosymmetric functions. Autosymmetry is a property that is frequent enough within Boolean functions to be interesting in the synthesis process. Each autosymmetric function can be synthesized through a new function (called restriction), depending on less variables and with a smaller on-set, which can be computed in polynomial time. In this paper we describe how to exploit the autosymmetry property of a Boolean function in order to obtain a smaller lattice representation in a reduced minimization time. The original Boolean function can be constructed through a composition of the restriction with some EXORs of subsets of the input variables. Similarly, the lattice implementation of the function can be constructed using some external lattices for the EXORs, whose outputs will be inputs to the lattice implementing the restriction. Finally, the output of the restriction lattice corresponds to the output of the original function. Experimental results show that the total area of the obtained lattices is often significantly reduced. Moreover, in many cases, the computational time necessary to minimize the restriction is smaller than the time necessary to perform the lattice synthesis of the entire function. Finally, we propose the application of this particular lattice composition technique, based on connected multiple lattices, to the synthesis on switching lattices of D-reducible Boolean functions, and to the more general framework of Preprint submitted to Embedded Hardware Design (Microprocessors and Microsystems)November 12, 2019 lattice synthesis based on logic function decomposition.

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Section: Introductionmentioning

confidence: 99%

Composition of switching lattices for regular and for decomposed functions

Bernasconi

Ciriani

Frontini

et al. 2018

Microprocessors and Microsystems

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“…Among the many three-level forms described in the literature [2], [1], [5], [9], [10], [11], [13], [15], [17], we focus on three-level EXOR-AND-OR forms, introduced in [7], [8], [13]. These forms, also known as Sum of Pseudoproducts or SPP, are a direct generalization of AND-OR forms, obtained generalizing cubes to pseudocubes where literals in cubes may be replaced by EXOR factors in pseudocubes.…”

Section: Introductionmentioning

confidence: 99%

2-SPP Approximate Synthesis for Error Tolerant Applications

Bernasconi

Ciriani

2014

2014 17th Euromicro Conference on Digital System Design

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We propose an approximate logic synthesis heuristic for synthesizing a 2-SPP circuit under a given error rate threshold. 2-SPP circuits are three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. They represent a direct generalization of SOP forms, obtained generalizing cubes to "2-pseudocubes" where literals in cubes may be replaced by 2-EXOR factors in 2-pseudocubes. We discuss and experimentally evaluate two different measures for the error: the bit threshold and the minterm threshold. The first metric considers the overall number of complemented output bits, while the second metric is related to the number of input vectors on which the output computed by the circuit is different from the exact one on at least one bit. Experimental results confirm the effectiveness of the proposed approach. For an error rate threshold of 1%, our heuristic for approximate 2-SPP synthesis provides an average reduction of the number of 2-pseudocubes in the cover of about 23% for all the considered benchmarks, when we consider the bit threshold error metric. The reduction in the number of 2-pseudocubes is interesting even in the minterm threshold error metric, especially when we perform the resynthesis of the derived approximate versions of the benchmarks: the average gain, without resynthesis is of about 8%, while the average gain with resynthesis becomes 15%.

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“…In our new approach will maintain the robust delay fault testability and whole design work on Functional mode with one control signals.In Section 2, the delay fault testability of network which explain the K-EPSOP form realization and projections of Boolean terms into the different spaces [1] and its implications on testability preservation. The pdf testability property using mux [11], BDD optimization [10],multi-valued minimization with PLA & output EXOR gate [5] and BDD based synthesis of symmetric circuit [9]. In Sections 2.B, we study the testability preservation of the K-EPSOP form path delay fault using muxes realization with remainder or without remainder.…”

Section: Introductionmentioning

confidence: 99%

Fully Robust Path Delay Fault Testability using KEPSOP

Sinsinwar¹,

Yadav²,

Acharya³

2011

IJCA

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Full testability is a desirable property network and maintaining the testability of multi-level logic synthesis is very complicated. In our paper propose new technique which maintains fully testable circuit with function mode under the robust path delay fault model. The preservation of testability of these networks under the stuck-at-fault model and Path delay model, preservation of testability the K-EPSOP is typical but it we proposed robust path delay fault model using binate property of variable with mux realization for remainder or without remainder. The whole our new architecture gives guarantees the path delay fault fully testable circuit a modification in design and operates on mode e.g. functional mode.

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Multiple-valued minimization to optimize PLAs with output EXOR gates

Abstract: Abstract

Cited by 23 publications

References 9 publications

Composition of switching lattices for regular and for decomposed functions

Composition of switching lattices for regular and for decomposed functions

2-SPP Approximate Synthesis for Error Tolerant Applications

Fully Robust Path Delay Fault Testability using KEPSOP

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