2-SPP Approximate Synthesis for Error Tolerant Applications

Abstract

We propose an approximate logic synthesis heuristic for synthesizing a 2-SPP circuit under a given error rate threshold. 2-SPP circuits are three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. They represent a direct generalization of SOP forms, obtained generalizing cubes to "2-pseudocubes" where literals in cubes may be replaced by 2-EXOR factors in 2-pseudocubes. We discuss and experimentally evaluate two different measures for the error: the bit threshold and the minterm threshold. The first metric considers the overall number of complemented output bits, while the second metric is related to the number of input vectors on which the output computed by the circuit is different from the exact one on at least one bit. Experimental results confirm the effectiveness of the proposed approach. For an error rate threshold of 1%, our heuristic for approximate 2-SPP synthesis provides an average reduction of the number of 2-pseudocubes in the cover of about 23% for all the considered benchmarks, when we consider the bit threshold error metric. The reduction in the number of 2-pseudocubes is interesting even in the minterm threshold error metric, especially when we perform the resynthesis of the derived approximate versions of the benchmarks: the average gain, without resynthesis is of about 8%, while the average gain with resynthesis becomes 15%.

Computing the full quotient in bi-decomposition by approximation

“…The method described in the previous sections is very general and can be applied to any approximation technique. In order to experimentally study the proposed approach, we discuss its application to a 0 → 1 known approximation method [2]. Thus, in this section we discuss the experimental results obtained by applying the techniques that require a 0 → 1 approximation of f (i.e., AND and ⇒, see Table II).…”

“…Since XOR gates are sensitive to some structural regularities of Boolean functions that are difficult to express using just AND and OR gates, they help when minimizing to derive more compact expressions. For technological reasons, SPP forms are further restricted to XOR factors with at most k literals [4], [5]; in particular, the approximation heuristic proposed in [2] and applied in this paper refers to SPP forms with k = 2, called 2-SPP forms [5], which exhibit a compact area, reduced delay (due to bounded number of levels), and reasonable synthesis time [1]. As an example, the function f represented by the Karnaugh map in Figure 2 (a) has a minimal SOP f SOP = x 1 x 3 x 4 + x 1 x 3 x 4 + x 2 x 3 x 4 +x 2 x 3 x 4 with 4 products and 12 literals, vs. a minimal 2-SPP expression f 2−SP P = x 1 (x 3 ⊕ x 4 ) + x 2 (x 3 ⊕ x 4 ), with only 2 pseudoproducts and 6 literals.…”

“…2-SPP forms can be over-approximated, as studied in [2], by expanding heuristically pseudoproducts by applying the following two steps: (i) evaluate the cost (i.e., the number of 0 → 1 complementations) and the gain of the expansion of each pseudoproduct in an initial 2-SPP cover of f ; and (ii) select the set of pseudoproducts whose expansion guarantees the maximum gain within a given error rate. As a fact, the expansion of pseudoproducts implies a reduction of literals in the algebraic expression; moreover, expanded pseudoproducts might cover some other pseudoproducts, which are removed from the cover.…”

Approximate Logic Synthesis by Symmetrization

“…Following the approach from [20], in [3] the concept of error rate has been further specialized with the notions of bit threshold B t and minterm threshold M t . The first metric evaluates the overall number of complemented (wrong) output bits, while the second metric evaluates the number of input vectors on which the output computed by the circuit differs from the exact one by at least one bit.…”

“…In recent years, many heuristic techniques for synthesizing approximate logic circuits have been investigated with promising results, see for instance [3], [5], [14], [15], [16], [20], [21], [22]. They derive approximate variants of a given combinational Boolean function, by modifying some of its outputs so that the modified circuit has a reduced complexity and power consumption, while the error is within the tolerance bounds (targeting two-level logic, XOR-AND-OR forms, multi-level logic, etc.…”