Composition of switching lattices for regular and for decomposed functions

Abstract

Multi-terminal switching lattices are typically exploited for modeling switching nano-crossbar arrays that lead to the design and construction of emerging nanocomputers. Typically, the circuit is represented on a single lattice composed by fourterminal switches. In this paper, we propose a two-layer model in order to further minimize the area of regular functions, such as autosymmetric and D-reducible functions, and of decomposed functions. In particular, we propose a switching lattice optimization method for a special class of "regular" Boolean functions, called autosymmetric functions. Autosymmetry is a property that is frequent enough within Boolean functions to be interesting in the synthesis process. Each autosymmetric function can be synthesized through a new function (called restriction), depending on less variables and with a smaller on-set, which can be computed in polynomial time. In this paper we describe how to exploit the autosymmetry property of a Boolean function in order to obtain a smaller lattice representation in a reduced minimization time. The original Boolean function can be constructed through a composition of the restriction with some EXORs of subsets of the input variables. Similarly, the lattice implementation of the function can be constructed using some external lattices for the EXORs, whose outputs will be inputs to the lattice implementing the restriction. Finally, the output of the restriction lattice corresponds to the output of the original function. Experimental results show that the total area of the obtained lattices is often significantly reduced. Moreover, in many cases, the computational time necessary to minimize the restriction is smaller than the time necessary to perform the lattice synthesis of the entire function. Finally, we propose the application of this particular lattice composition technique, based on connected multiple lattices, to the synthesis on switching lattices of D-reducible Boolean functions, and to the more general framework of Preprint submitted to Embedded Hardware Design (Microprocessors and Microsystems)November 12, 2019 lattice synthesis based on logic function decomposition.

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

“…It can be observed from Table I that there exist a number of possible lattices to realize a given logic function, enabling the designer to choose the most appropriate one that fits best in the design. In recent years, efficient algorithms have been introduced for the synthesis of logic functions using switching lattices [2]- [4], [13]. These algorithms realize a logic function by simply mapping the appropriate literals of the logic function and/or constant values (0 and 1) to the control inputs of switches.…”

“…While developing the technology, we consider two main criteria: 1) considering the symmetry among four terminals, the I-V relationship of terminal pairs should be similar to each other; 2) a single gate to control all current paths between terminal pairs. Since there are 6 possible pair of terminals, computed as C (4,2), where C stands for the combinations, we have 6 different current paths or channels. Note that in a conventional CMOS transistor, there is a single current path between its source and drain terminals.…”

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

“…Note that not every logic function can be represented in the D-reducible form. Similarly, the methods of [9], [10] exploit the p-circuits and autosymmetric form of a target function, respectively and use the algorithms of [3], [6] to find a solution on the decomposed smaller functions. In [10], the target function is synthesized with multiple lattices sharing the common ones, but adding extra logic gates which may not be desirable due to the wires between these gates and lattice control inputs.…”

“…Similarly, the methods of [9], [10] exploit the p-circuits and autosymmetric form of a target function, respectively and use the algorithms of [3], [6] to find a solution on the decomposed smaller functions. In [10], the target function is synthesized with multiple lattices sharing the common ones, but adding extra logic gates which may not be desirable due to the wires between these gates and lattice control inputs. The method of [11] determines a number of promising lattice candidates and uses a method of [6] to find if one of these lattices leads to a solution.…”

Testability of Switching Lattices in the Cellular Fault Model

“…The first description of lattices for implementing Boolean functions is due to a seminal paper by Akers in 1972 [1]. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, synthesis methods targeting lattices of multi-terminal switches have found a renewed interest [2], [3], [4], [5], [7], [8], [10], [11], [12].…”