Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Safaltın, Şerzat; Gencer, Oğuz; Morgül, M. Ceylan; Aksoy, Levent; Gürmen, Sebahattin; Moritz, Csaba Andras; Altun, Mustafa

doi:10.23919/date.2019.8715123

Cited by 11 publications

(11 citation statements)

References 16 publications

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“…In this figure, T1, T2, T3, and T4 stand for the four terminals. Further details on the technology development can be found in [13]. It is confirmed through technology simulations that these devices behave as a four-terminal switch.…”

Section: Introductionmentioning

confidence: 77%

“…Moreover, the SAT problem complexity increases as the lattice size increases because the number of products and degree of the lattice function increase as shown in Tables 1 and 2. For example, for 7-XOR to be realized using the 6 × 6 (7 × 6) lattice, the SAT problem has 220,866 (844,372) variables and 3,016,945 (13,808,368) clauses. This analysis clearly indicates that the performance of JANUS depends heavily on the number of literals and products of the target function and lattice size.…”

Section: Sat Problem Complexitymentioning

confidence: 99%

“…It is shown in [13] that a four-terminal switch can be developed using the conventional CMOS technology and can be used to form a switching lattice. Fig.…”

Section: Introductionmentioning

confidence: 99%

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Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Aksoy

Altun

2020

IEEE Trans. Comput.

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Two-dimensional switching lattices including four-terminal switches are introduced as alternative structures to realize logic functions, aiming to outperform the designs consisting of one-dimensional two-terminal switches. Exact and approximate algorithms have been proposed for the problem of finding a switching lattice which implements a given logic function and has the minimum size, i.e., a minimum number of switches. In this article, we present an approximate algorithm, called JANUS, that explores the search space in a dichotomic search manner. It iteratively checks if the target function can be realized using a given lattice candidate, which is formalized as a satisfiability (SAT) problem. As the lattice size and the number of literals and products in the given target function increase, the size of a SAT problem grows dramatically, increasing the run-time of a SAT solver. To handle the instances that JANUS cannot cope with, we introduce a divide and conquer method called MEDEA. It partitions the target function into smaller sub-functions, finds the realizations of these sub-functions on switching lattices using JANUS, and explores alternative realizations of these sub-functions which may reduce the size of the final lattice. Moreover, we describe the realization of multiple functions in a single lattice. Experimental results show that JANUS can find better solutions than the existing approximate algorithms, even than the exact algorithm which cannot determine a minimum solution in a given time limit. On the other hand, MEDEA can find better solutions on relatively large size instances using a little computational effort when compared to the previously proposed algorithms. Moreover, on instances that the existing methods cannot handle, MEDEA can easily find a solution which is significantly better than the available solutions.

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Section: Introductionmentioning

confidence: 77%

Section: Sat Problem Complexitymentioning

confidence: 99%

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Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Aksoy

Altun

2020

IEEE Trans. Comput.

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“…Switching lattices have been proposed as key structures to synthesize logic functions, aiming to achieve significant gains on area, delay, and power consumption with respect to designs using traditional two-terminal switches [3], [4]. From a technological perspective, it is indicated in [3] that switching lattices fit perfectly in emerging technologies, such as nanowire and spin-wave crossbar structures and it is shown in [5] that the conventional CMOS technology can be used to implement switching lattices.…”

Section: Introductionmentioning

confidence: 99%

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Aksoy

Altun

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In recent years the realization of a logic function on two-dimensional arrays of four-terminal switches, called switching lattices, has attracted considerable interest. Exact and approximate methods have been proposed for the problem of synthesizing Boolean functions on switching lattices with minimum size, called lattice synthesis (LS) problem. However, the exact method can only handle relatively small instances and the approximate methods may find solutions that are far from the optimum. This paper introduces an approximate algorithm, called JANUS, that formalizes the problem of realizing a logic function on a given lattice, called lattice mapping (LM) problem, as a satisfiability problem and explores the search space of the LS problem in a dichotomic search manner, solving LM problems for possible lattice candidates. This paper also presents three methods to improve the initial upper bound and an efficient way to realize multiple logic functions on a single lattice. Experimental results show that JANUS can find solutions very close to the minimum in a reasonable time and obtain better results than the existing approximate methods. The solutions of JANUS can also be better than those of the exact method, which cannot be determined to be optimal due to the given time limit, where the maximum gain on the number of switches reaches up to 25%.

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“…Four terminal architecture has either all of its terminals connected or disconnected. The desired state is actualized with a controlling input, which is not present in the Figure 1(c) and has a separate physical formation from the crossbar which is thoroughly explained for different technologies in [6] [30]. Detailed TCAD simulations and technology development are presented in [30].…”

mentioning

confidence: 99%

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Morgül

Frontini

Tunali

et al. 2021

IEEE Trans. Nanotechnology

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Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS with the drawback of higher fault rates. They offer area and power efficiency in terms of their easy-to-fabricate and dense physical structures. They consist of regularly placed crosspoints as computing elements, which behave as diode, memristor, field effect transistor, or novel four-terminal switching devices. In this study, we establish a complete design framework for crossbar circuits explaining and analyzing every step of the process. We comparatively elaborate on these technologies in the sense of their capabilities for computation regarding area including a new logic synthesis technique for memristors, fault tolerance including a novel paradigm for four-terminal devices, delay, and power consumption. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and fault rates of the given crossbar as well as their effects on performance metrics including power, delay, and area.

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Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Cited by 11 publications

References 16 publications

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

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