Fully Robust Path Delay Fault Testability using KEPSOP

Abstract

Full testability is a desirable property network and maintaining the testability of multi-level logic synthesis is very complicated. In our paper propose new technique which maintains fully testable circuit with function mode under the robust path delay fault model. The preservation of testability of these networks under the stuck-at-fault model and Path delay model, preservation of testability the K-EPSOP is typical but it we proposed robust path delay fault model using binate property of variable with mux realization for remainder or without remainder. The whole our new architecture gives guarantees the path delay fault fully testable circuit a modification in design and operates on mode e.g. functional mode.