Multiband UWB transceivers

Razavi, Behzad; Aytur, T.; Lam, Carly Siu Yin; Yang, Fei; Yan, Ran; Kang, Han-Chang; Hsu, Ching-Ting; Lee, Chao-Cheng

doi:10.1109/cicc.2005.1568628

Cited by 23 publications

(9 citation statements)

References 6 publications

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“…To achieve a better IRR, the amplitude and phase imbalances should be restricted to be within a tight range (e.g. α < 0.1 dB and θ < 1 degree for 40 dBc IRR) [21]. In general, minimizing the I/Q mismatch can improve EVM.…”

Section: B the Influence Of I/q Impairmentmentioning

confidence: 99%

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

et al. 2020

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This paper describes a direct-conversion E-band transmitter (TX) in 65-nm CMOS. To demonstrate the feasibility of E-band 1024-quadrature amplitude modulation (QAM), a 67 to 86 GHz direct-conversion CMOS transmitter with broadband image rejection is presented. The transmitter contains an I (in-phase) and Q (quadrature-phase) modulator and a five-stage power amplifier. To achieve a 40 dBc image-rejection ratio (IRR) of the I/Q modulator for E-band, a broadband half-quadrature generator (HQG), which contains a composite right/left-handed (CRLH) based divider, quadrature couplers, and baluns is proposed. For the purpose of minimizing the phase imbalance, phase balance lines are utilized in HQG to achieve a 1-degree phase accuracy under different tuning lines. Subsequently, the reflection can be mitigated by optimizing the impedance matching between the HQG and the mixer core. Meanwhile, because millimeter-wave (MMW) circuits are susceptible to process variations, a process-variation-tolerant design is introduced to mitigate IRR variation, especially under 40 dBc. The transmitter demonstrates a measured flat conversion gain (CG) of 23 ± 2 dB from 56 to 86 GHz. The proposed TX achieves an IRR better than 40 dBc from 67 to 86 GHz (bandwidth of 19 GHz) with a peak IRR of 56.2 dBc at 70 GHz. Furthermore, the proposed TX has exhibited a 6 bit/s/Hz spectral efficiency with 1024-QAM under the orthogonal frequency-division multiplexing (OFDM) modulation format. The 1.129 mm 2 E-band TX achieves a measured output power of 6.5 dBm with a total dc power consumption of 164 mW from a 1.2 V supply voltage. INDEX TERMS CMOS, E-band, half-quadrature generator (HQG), image-rejection ratio (IRR), millimeter-wave (MMW) integrated circuit, process-variation-tolerant design, transmitter (TX), 1024-quadrature amplitude modulation (QAM).

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Section: B the Influence Of I/q Impairmentmentioning

confidence: 99%

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

et al. 2020

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“…An increased number of wideband wireless communication standards and well-advanced optical communications have put stringent requirements on the speed, resolution, and power consumption of analog-to-digital converters [1]- [2]. Nyquistrate ADCs like the Pipeline and Flash architectures have been used in high-speed applications where resolution is less important than conversion rate.…”

Section: Introductionmentioning

confidence: 99%

A 2 GHz effective sampling frequency K-Delta-1-Sigma analog-to-digital converter

Labaziewicz

Baker

2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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As CMOS technology scales to nanometer dimensions, analog-to-digital converter (ADC) design has become increasingly more challenging. This is mainly due to the increased transistor leakage currents, process variations, and poor matching. The K-Delta-1-Sigma (KD1S) modulator was proposed as a practical solution for designing high-speed ADCs in nanometer CMOS processes. This paper presents an 8-path KD1S modulator with an effective sampling frequency of 2 GHz derived from a 250 MHz input clock. The simulation results confirm the true first-order noise shaping of the modulator. The simulated SNR is 44.95 dB and the simulated SNDR is 44.41 dB corresponding to N eff = 7.17 bits with a conversion bandwidth of 15.625 MHz.

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“…Due to the different regulatory frequency band of each country, a UWB transceiver that supports the 14 bands (Band group 1, 2, 3, 4, 5) is more required. A frequency synthesizer that includes the 12 bands (3.1GHz to 9.5GHz) was introduced [2]. In [3], a Ins fast-hopping multi-tone generator based on the two PLLs and a single side-band (SSB) mixer is presented.…”

Section: Introductionmentioning

confidence: 99%

Fast Settling 9GHz PLL Using 528MHz Reference PLL Clock for MB-OFDM UWB System

Lee

Hyun

Tak

et al. 2006

2006 European Microwave Integrated Circuits Conference

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A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336-8.976GHz in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in the multi-band orthogonal frequency division multiplexing (OFDM) because the frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, the integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at the 9GHz and 528MHz are integrated and shows the band hopping lower than lns.Index Terms -Phase locked loops, CMOS analog integrated circuits, Voltage controlled oscillators.

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Multiband UWB transceivers

Cited by 23 publications

References 6 publications

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

A 2 GHz effective sampling frequency K-Delta-1-Sigma analog-to-digital converter

Fast Settling 9GHz PLL Using 528MHz Reference PLL Clock for MB-OFDM UWB System

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