A 2 GHz effective sampling frequency K-Delta-1-Sigma analog-to-digital converter

Abstract

As CMOS technology scales to nanometer dimensions, analog-to-digital converter (ADC) design has become increasingly more challenging. This is mainly due to the increased transistor leakage currents, process variations, and poor matching. The K-Delta-1-Sigma (KD1S) modulator was proposed as a practical solution for designing high-speed ADCs in nanometer CMOS processes. This paper presents an 8-path KD1S modulator with an effective sampling frequency of 2 GHz derived from a 250 MHz input clock. The simulation results confirm the true first-order noise shaping of the modulator. The simulated SNR is 44.95 dB and the simulated SNDR is 44.41 dB corresponding to N eff = 7.17 bits with a conversion bandwidth of 15.625 MHz.

High speed time-multiplexed continuous time Sigma-Delta converters

“…Block Digital Filtering [1], Hadamard Σ∆ modulation [2], and K-Delta-1-Sigma modulation [3] are some of the techniques mentioned in literature as 'time-multiplexed' Sigma-Delta converters. Despite their high gain in SNR (signalto-noise ratio), extra complex blocks are needed next to the Sigma-Delta converters in each channel, which sometimes need to fulfill high speed-requirements.…”

“…Despite their high gain in SNR (signalto-noise ratio), extra complex blocks are needed next to the Sigma-Delta converters in each channel, which sometimes need to fulfill high speed-requirements. Furthermore, literature shows that channel mismatch in these time-multiplexed converters is important [3].…”