Multi-V&lt;inf&gt;T&lt;/inf&gt; engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide

Singanamalla, R.; Boccardi, G.; Tseng, Jeng‐Sen; Pétry, J.; Vellianitis, G.; Dal, M.J.H. van; Duriez, B.; Vecchio, Guglielma; Bulle-Lieuwma, C.W.T.; Berkum, J. van; Lander, R.J.P.; Müller, Markus

doi:10.1109/vtsa.2010.5488925

Cited by 3 publications

(2 citation statements)

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“…Owing to the lack of a back-gate bias option in fully depleted FinFET devices, complicated WF engineering is required to achieve multiple V th solution for undopped FinFET [14], [16], [17]. Ion implantation into metal gatestack of TiN/HfO2 provides suitable VT for devices keeping channel undopped.…”

Section: Methodology For Vt-targeting Using Work Function Tuningmentioning

confidence: 99%

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Sakhare

Miyaguchi

Raghavan

et al. 2015

IEEE Trans. Electron Devices

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For the first time, we present complete device threshold voltage (VT)-targeting methodology for FinFET SRAM in 10-nm technology, considering capacitance due to metal pattering and device variability to set target read current for different variants of SRAM architecture to determine technology highdensity (HD) SRAM cell. The VT-targeting methodology brings into play the worst case read and write margins available for SRAM cell to determine nominal device VT by tuning the work function of metal gate. Analysis shows that for minimum leakage current, 112 SRAM cell is optimum, whereas for the same area of 0.0546 μm 2 with 50% higher leakage, 122 SRAM outperform by 5% and 20% improved read and write margins, respectively. The 122 SRAM as HD cell reduces the cost of the technology by sharing P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) VT mask with the high threshold voltage logic devices, whereas the 112 SRAM device shares only NFET VT mask. The 111 SRAM can achieve target performance at lesser area of 0.048 μm 2 by compromising read stability, which will result in lower yield. At 64-nm pitch, litho-etch litho-etch (LELE) double-patterned gate impacts device performance and alleviates variability; hence the read margin of SRAM cell should consider an additional 1σ rsnm margin to retain the same yield in 10-nm-technology era.Index Terms-10-nm technology, design methodology, design technology co-optimization (DTCO), double patterning gate, FinFET SRAM design, high density (HD), selfaligned double patterning (SADP), self-aligned quadruple patterning (SAQP), SRAM threshold voltage (VT) targeting, technology SRAM.

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Section: Methodology For Vt-targeting Using Work Function Tuningmentioning

confidence: 99%

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Sakhare

Miyaguchi

Raghavan

et al. 2015

IEEE Trans. Electron Devices

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“…Threshold voltage modulation in low-power applications has being realized by the use of complicated processes such as a combination of several metals having different work functions, ion implantation on the gate work function metals, and depositing a capping layer to make dipoles within the gate dielectric layer. [17][18][19][20] However, these schemes not only require complicated processes but also are not cost effecive. 5) But PLAD is a low-cost process and with it higher doping concentrations can be realized than with ion implantation.…”

Section: Introductionmentioning

confidence: 99%

Analysis of gate-induced drain leakage characteristics and threshold voltage modulation of plasma-doped FinFETs for low-power applications

Lee

Cho

Kim

et al. 2016

Jpn. J. Appl. Phys.

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FinFET devices were fabricated using plasma doping both at the source and drain extensions and in the channel region. In an effort to overcome dopant loss after the strip process, oxide buffer layers were deposited prior to plasma doping. Owing to the oxide buffer, 76% of the dopants were retained after the strip process and even after ashing, thereby keeping a high doping concentration of over 1 × 1020 atoms/cm3 on the surface of the Si fin. The gate-induced drain leakage (GIDL) current was decreased by 2 orders of magnitude due to the shallow and abrupt plasma doping, compared to the performance with an ion implantation method. The threshold voltage (V th) was shifted by 250 mV through plasma doping of the channel. The doping conformality was evaluated using electrical measurements and a newly-proposed method based on the GIDL data with various fin widths. The conformal doping profile with a smaller dopant loss provides a smaller GIDL current.

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Understanding the FinFET Mobility by Systematic Experiments

Akarvardar

Young

Baykan

et al. 2013

Lecture Notes in Nanoscale Science and Technology

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Multi-V<inf>T</inf> engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide

Cited by 3 publications

References 0 publications

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era

Analysis of gate-induced drain leakage characteristics and threshold voltage modulation of plasma-doped FinFETs for low-power applications

Understanding the FinFET Mobility by Systematic Experiments

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