Analysis of gate-induced drain leakage characteristics and threshold voltage modulation of plasma-doped FinFETs for low-power applications

Abstract

FinFET devices were fabricated using plasma doping both at the source and drain extensions and in the channel region. In an effort to overcome dopant loss after the strip process, oxide buffer layers were deposited prior to plasma doping. Owing to the oxide buffer, 76% of the dopants were retained after the strip process and even after ashing, thereby keeping a high doping concentration of over 1 × 1020 atoms/cm3 on the surface of the Si fin. The gate-induced drain leakage (GIDL) current was decreased by 2 orders of magnitude due to the shallow and abrupt plasma doping, compared to the performance with an ion implantation method. The threshold voltage (V th) was shifted by 250 mV through plasma doping of the channel. The doping conformality was evaluated using electrical measurements and a newly-proposed method based on the GIDL data with various fin widths. The conformal doping profile with a smaller dopant loss provides a smaller GIDL current.

Improved physical models for advanced silicon device processing

“…Classical standard doping techniques like ion implantation may not be suitable for FinFET devices because of the 3D geometry. Several solutions to incorporate dopants in the fin are being explored such as tilted ion implantation [23,153,158], plasma doping [159][160][161][162] or vapor phase doping [163]. Among them, tilted ion implantation remains a strong candidate to introduce dopants into the fin, as it is a conventional and well established technique, although it suffers from specific issues that arise from the particular geometry of these devices.…”

“…Alternatively, plasma doping has gained interest due to the higher levels of conformality of fin doping and the lower levels of damage in the fin that can be achieved when compared to ion implantation, although it is also quite challenging due to secondary effects (sputtering/erosion, traps generation, etc.) that need to be addressed [19,161,162].…”

“…Nevertheless, conformal doping is more difficult for n-type doping. This is due to the low adsorption efficiency of n-type dopants on Si surfaces that results in poor incorporation of As or P on the fin sidewalls [18,19,160,162,180]. Dopants located at the fin surface are then vulnerable to subsequent resist strip and etching processes (i.e.…”

“…Dopants located at the fin surface are then vulnerable to subsequent resist strip and etching processes (i.e. dopant losses for As doped fins from 75% [180] to a recently improved value of around 25% after the strip process have been reported [162]). To avoid dopant loss after the strip process, recent studies considered the use of a rapid thermal annealing (RTA) after plasma doping in order to drive the dopants inside the fin (in-diffusion) and electrically activate them [18,19].…”

“…More recently, Lee et al have considered the deposition of an oxide buffer layer prior to plasma doping instead of RTA, achieving about 76% of the As doped concentration retained in the Si fin after the strip process and even after ashing [162]. Nevertheless, although recent works on plasma doping in FinFETs are promising in terms of dopant incorporation and conformality, this technique is still quite challenging.…”