Multi-domain clock skew scheduling

Abstract

Abstract

Latch-Based Performance Optimization for FPGAs

“…For example, for a combinational logic path from a flip-flop j to flip-flop i, clock skew scheduling may delay the arrival of the clock signal to i, thereby allowing more time for a logic signal to arrive at i's input. Recent research [2]- [4] has shown that only a few skewed clocks are necessary to obtain appreciable improvements in circuit speed. Unfortunately, clocks comprise 20-39% of dynamic power consumption in commercial FPGAs [5], [6] and FPGAs already consume 7-14× more dynamic power than ASICs [7].…”

“…Although extra clock lines are not required to borrow time, the practical usage of retiming is limited due to its impact on the verification methodology, i.e., equivalence checking and functional simulation [2]. Retiming can change the number of flip-flops in a design, for example, in the case of moving a flip-flop "upstream" from the output of a multi-input logic gate to its inputs.…”

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

“…Recently, multi-domain clock skew scheduling has been proposed in [12]. Multiple clocking domains are routinely used in designs to realize target clock frequency and also to address specific timing requirements.…”

“…The motivation behind the multi-domain skew scheduling is based on the fact that large phase shifts between clocking domains can be implemented reliably by using dedicated, possibly expensive circuit components such as "structured clock buffers" [13]. In [12], Ravindran et al showed that a clock skew schedule using a few domains combined with a small within-domain latency can reliably implement the full optimization potential of clock skew scheduling. They proposed an algorithm based on a branch-and-bound search to assign registers to clock domains and also they modified Burns' algorithm [14] to compute the skew values.…”

“…Clock skew schedulers [5], [9], [12] on the other hand, view the clock skew as a manageable resource rather than a liability. They intentionally introduce skews to registers to improve the circuit performance.…”