2011 21st International Conference on Field Programmable Logic and Applications 2011
DOI: 10.1109/fpl.2011.21
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Latch-Based Performance Optimization for FPGAs

Abstract: Abstract-We explore using pulsed latches for timing optimization -a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do not have the power or area drawbacks associated with other timing optimization approaches, such as clock skew and retiming. We propose an algorithm that iteratively replaces certain flip-flops in a logic desig… Show more

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Cited by 6 publications
(2 citation statements)
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“…Pulse latches can also be used to perform small amounts of time borrowing between consecutive sequential paths. The use of latches in FPGAs to support time borrowing has also been explored in [15,18] with positive results in performance improvement. In contrast to selectively using pulse latches, we provided ubiquitous pulse latches in the Stratix V logic fabric.…”
Section: Time-borrowing Flip-flopsmentioning
confidence: 98%
“…Pulse latches can also be used to perform small amounts of time borrowing between consecutive sequential paths. The use of latches in FPGAs to support time borrowing has also been explored in [15,18] with positive results in performance improvement. In contrast to selectively using pulse latches, we provided ubiquitous pulse latches in the Stratix V logic fabric.…”
Section: Time-borrowing Flip-flopsmentioning
confidence: 98%
“…Gunawardena noted that many of the results proved in [3,18] are instances of general theorems in max-plus algebra. Nearly twenty years on, max-plus methods do not appear to be widespread amongst the timing analysis community, with only a handful of papers in this area [15,16,20]. We believe that these methods have great potential to be exploited.…”
Section: Introductionmentioning
confidence: 99%