Multi-chip packaging technology for VLSI-based systems

Levinstein, H. J.; Bartlett, Charles; Bertram, W.J.

doi:10.1109/isscc.1987.1157100

Cited by 31 publications

(2 citation statements)

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“…Although the full potential of advanced hybrid packaging will have to be developed, the advantages are already seen in the ceramic substrate packaging approach" and the silicon substrate, multi-chip packaging modules. 25 Passive substrates retain one limitation of conventional packaging, namely inefficient integration of drivers, multiplexers, transceivers, and other communication circuitry. Such small-scale circuit functions might be integrated on VLSI circuits, although power limits and I/O limits are serious constraints.…”

Section: New Interconnection-based Technologiesmentioning

confidence: 99%

Fundamental Interconnection Issues

Hornak¹,

Little²,

Tewksbury³

et al. 1987

At&T Technical Journal

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This paper presents several current interconnection issues as well as future technological directions for improved interconnection/communication performance. The physical hierarchy of interconnections and the corresponding communication environment are highlighted. General issues concerning chip‐to‐chip and on‐chip interconnections are reviewed, with particular emphasis on chip or wafer‐level clock distribution. Finally, wafer‐scale related system modules and optical interconnections are discussed from a “macro‐integration” perspective.

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Section: New Interconnection-based Technologiesmentioning

confidence: 99%

Fundamental Interconnection Issues

Hornak¹,

Little²,

Tewksbury³

et al. 1987

At&T Technical Journal

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“…In this process, solder is applied to the contact pads of chip and substrate wafers byevaporation through a metal mask before reflow assembly. [1][2][3][4] For gated-diode cross-point (GDX) devices in 5ESS® switching systems, spherical solder preforms are attached directly to the metallized pads ofleadless chip carriers. These solder-bumped chip carriers are then surface-mounted on ceramic substratesof hybridintegrated-circuit modules.…”

Section: Introductionmentioning

confidence: 99%

Automated Visual Inspection of Solder Bumps

Ray

1988

At&T Technical Journal

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This paper describes a computer vision technique for automated inspection of solder bumps on leadless chip carriers and metallized wafers for advanced VLSI (very‐large‐scale integration) packaging. It is based on high‐contrast imaging of soldered surfaces against a reflective background using dark‐field illumination for selective enhancement of surface topography. A brightfield image is also used for resolving ambiguities in image understanding. Gray‐scale images are analyzed using vision algorithms to detect topographic discontinuities of soldered surfaces and to identify solder‐bump defects.

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