MOSFET modeling for low noise, RF circuit design

Deen, M. Jamal; Chen, Chih‐Hung; Cheng, Yuhua

doi:10.1109/cicc.2002.1012797

Cited by 25 publications

(16 citation statements)

References 19 publications

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“…4c and 6c). What we do take into account, again in agreement with Deen et al, 16 is channel length modulation, i.e., the effect that the electrical channel length L elec is decreased by the length of the pinch-off region, depending on the gate-source and drain-source voltage applied to the device.…”

Section: Drain Current Noisesupporting

confidence: 52%

“…The details of the derivation of S ID can be found elsewhere. 11 It was argued recently by Jamal Deen et al 16 that the possible noise contribution of the pinch-off region is negligible. In our model we also neglect this contribution, which is corroborated by the experimental observation that there is hardly any dependence of the noise on V DS beyond the saturation voltage (see Section 3, Figs.…”

Section: Drain Current Noisementioning

confidence: 99%

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Compact modeling of noise for RF CMOS circuit simulation

et al. 2003

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We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 µm CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

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Section: Drain Current Noisesupporting

confidence: 52%

Section: Drain Current Noisementioning

confidence: 99%

Compact modeling of noise for RF CMOS circuit simulation

et al. 2003

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“…For example, if is large and is small, the second term in (2) will be large and will be the subtraction of two large numbers; hence, this will lead to be very sensitive to measurement errors. Furthermore, the accuracy of measured will, in turn, affect the extraction of the parameter in (1). Therefore, it is expected that for measurement of small device sizes with low values, their is typically less than 1 dB.…”

Section: B Atn Np5 Measurement Theorymentioning

confidence: 99%

“…9(a). This is mainly due to the higher output conductance when increases at a fixed biasing point [1]. As is mainly the coupled thermal noise from the channel through the gate capacitance to the gate structure, it is strongly dependent on the gate capacitance and is less sensitive to the biasing applied in the channel.…”

Section: B Atn Np5 Measurement Theorymentioning

confidence: 99%

“…Although HF noise modeling has been widely studied and researched, in most of the published papers, they mainly demonstrated HF noise model fitting at a fixed device size and a few biasing points [1]- [6]. The objective of this paper is to demonstrate scalable HF noise modeling for RFCMOS for a range of geometry sizes, biasing, and frequency points.…”

Section: Introductionmentioning

confidence: 98%

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A Scalable RFCMOS Noise Model

Tong

Lim

Yeo

et al. 2009

IEEE Trans. Microwave Theory Techn.

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This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time.Index Terms-BSIM3v3, high-frequency (HF) noise model, HF noise modeling, RF MOSFET, RFCMOS, Verilog-A.

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Channel noise enhancement in small geometry MOSFET and its influence on phase noise calculation of integrated voltage‐controlled oscillator

Kojima

Ohguro

2005

Int J Numerical Modelling

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SUMMARYChannel noise enhancement due to MOSFET scaling and its influence on phase noise estimation of fully integrated VCO have been studied. The channel noise of MOSFET increases due to the hot electron effect of small geometry MOSFET is obvious. The channel noise coefficient, g; of NMOS is 3.5 for 40-nm gate length, 2.0 for 90-nm gate length in spite of being 2 3 for long channels MOSFET. Simultaneously, calculation of phase noise of fully integrated VCO shows large difference using g ¼ 2 3 because the part of noise performance of VCO gain-cell depends on channel noise of MOSFET. Calculated phase noise showed good agreement with measured data when the optimum value of channel noise of MOSFET was adopted.

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MOSFET modeling for low noise, RF circuit design

Cited by 25 publications

References 19 publications

Compact modeling of noise for RF CMOS circuit simulation

Compact modeling of noise for RF CMOS circuit simulation

A Scalable RFCMOS Noise Model

Channel noise enhancement in small geometry MOSFET and its influence on phase noise calculation of integrated voltage‐controlled oscillator

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