A Scalable RFCMOS Noise Model

Tong, Aijun; Lim, Wei Meng; Yeo, Kiat Seng; Sia, Choon Beng; Zhou, Wen Cong

doi:10.1109/tmtt.2009.2017245

Cited by 19 publications

(14 citation statements)

References 12 publications

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“…The process parameters in tsmc™ 90 nm CMOS process are listed as follows: the of PMOS is 0.44 nV at 10 MHz, and . The value for a short channel device is about 1 [29]. The power gain is 12 dB.…”

Section: B Conversion Gain Noise Figure and Linearitymentioning

confidence: 97%

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

Chiou

Lin

Chen

et al. 2012

IEEE Trans. Circuits Syst. I

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A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP ) and IIP are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP and the IIP of the DCR are 33 dBm and dBm, respectively.Index Terms-AC coupling, CMOS, current reuse, direct-conversion receiver, double balanced mixer, folded-switch mixer, low voltage.

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Section: B Conversion Gain Noise Figure and Linearitymentioning

confidence: 97%

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

Chiou

Lin

Chen

et al. 2012

IEEE Trans. Circuits Syst. I

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“…Both are presented in (5) with G n representing the thermal noise conductance (g n is its normalized value). n n dso m δ= , γ= G G G G (5) δ is evaluated for zero V DS , thus it has no specific meaning in terms of RFIC design.…”

Section: Thermal Noise Excess Factormentioning

confidence: 99%

CMOS RF noise, scaling, and compact modeling for RFIC design

Antonopoulos

Bucher

Papathanasiou

et al. 2013

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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This work presents an analysis of high frequency noise and linearity performance of a 90 nm CMOS process. Measurements are performed for a wide range of nominal gate lengths and bias points at high frequency. Modeling is based on the EKV3 compact model in Spectre RF circuit simulator from Cadence. The model shows correct scalability for noise and linearity accounting for short channel effects (SCEs), such as velocity saturation (VS) and channel length modulation (CLM). Results are presented versus a common measure of channel inversion level, named inversion coefficient. Optimum performance is shown to gradually shift from higher to lower levels of moderate inversion, when scaling from 240 nm to 100 nm. The same trend is observed from investigating the transconductance frequency product (TFP) of a common-source (CS) LNA for technology nodes ranging from 180 nm to 22 nm.Index Terms -Compact model, distortion analysis, dynamic range, high frequency noise, metal oxide semiconductor field effect transistor (MOSFET), minimum noise figure (NF min ), moderate inversion.

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“…This approach has been widely used for many years since it allows a considerable reduction of the gate resistance . The importance of reducing relies on the fact that this parameter negatively impacts figures-of-merit such as the noise figure and the maximum frequency of oscillation [2]- [4]. Consequently, much research has been dedicated to characterize and repre- sent this important parameter for modeling purposes [5], [6], but also to provide information to develop improved devices [7].…”

Section: Introductionmentioning

confidence: 99%

Modeling the Impact of Multi-Fingering Microwave MOSFETs on the Source and Drain Resistances

Zarate-Rincon

Murphy‐Arteaga

Torres‐Torres

et al. 2014

IEEE Trans. Microwave Theory Techn.

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Modern MOSFETs operated at high frequencies are designed and fabricated using a multi-fingered structure to enhance performance, especially to reduce gate resistance. However, even though the layout-dependent effect of other parasitics, such as that related to the source and drain resistances, is becoming more important, it has not been extensively investigated at high frequencies. In this paper, source and drain resistances are experimentally determined and analyzed for several microwave MOSFETs to characterize their corresponding dependence on the layout. This allows for the quantification and modeling of the impact of the device's geometry on its parasitic extrinsic parameters. Physically based closed-form equations are proposed here to accurately represent -parameters of MOSFETs operating at microwave frequencies with layouts considering different numbers of gate fingers, and grouping devices in cells with multiple source and drain junctions. The proposed models are compatible with SPICE-like circuit simulators, and an excellent model-experiment correlation is obtained when using the proposed scalable equations to represent different geometry MOSFETs up to 60 GHz.

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A Scalable RFCMOS Noise Model

Cited by 19 publications

References 12 publications

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

CMOS RF noise, scaling, and compact modeling for RFIC design

Modeling the Impact of Multi-Fingering Microwave MOSFETs on the Source and Drain Resistances

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