Modeling the Impact of Multi-Fingering Microwave MOSFETs on the Source and Drain Resistances

Abstract

Modern MOSFETs operated at high frequencies are designed and fabricated using a multi-fingered structure to enhance performance, especially to reduce gate resistance. However, even though the layout-dependent effect of other parasitics, such as that related to the source and drain resistances, is becoming more important, it has not been extensively investigated at high frequencies. In this paper, source and drain resistances are experimentally determined and analyzed for several microwave MOSFETs to characterize their corresponding dependence on the layout. This allows for the quantification and modeling of the impact of the device's geometry on its parasitic extrinsic parameters. Physically based closed-form equations are proposed here to accurately represent -parameters of MOSFETs operating at microwave frequencies with layouts considering different numbers of gate fingers, and grouping devices in cells with multiple source and drain junctions. The proposed models are compatible with SPICE-like circuit simulators, and an excellent model-experiment correlation is obtained when using the proposed scalable equations to represent different geometry MOSFETs up to 60 GHz.

The large world of FET small-signal equivalent circuits (invited paper)

“…The extrinsic elements are usually assumed to be bias independent, making their determination much easier. However, it should be underlined that many studies have been conducted to investigate the bias dependence of R s and R d for different FET technologies . Furthermore, to taken into account for the distributed effects playing a more significant role at operating frequencies as high as W‐band (75–110 GHz), the extrinsic capacitances are often split into two equal parts placed outermost and innermost of the three extrinsic inductances .…”

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

“…Optimized multi-fingered transistor layouts are widely used to reduce gate resistance and to increase maximum frequency of oscillation ( f max ). The RFSOI's market trends for production designs show that there is an urgent requirement for a robust compact model, which can capture FDSOI transistor behavior accurately at high frequency ranges [11].…”