Compact modeling of noise for RF CMOS circuit simulation

Abstract

We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 µm CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

Drifting-Dipole Noise (DDN) Model of MOSFETs for Microwave Circuit Design

“…Recent report by Navid et al [4] employed a ballistic-based model and hydrodynamic simulator to explain the excess thermal noise in the nanoscale MOSFET was due to partial suppression of shot noise. Nevertheless, the results of the hypothesis was inconsistent with the experimental noise data previously reported [5], [6] for scaled devices. In general, recent published results on a conventional bulk MOSFET also shared similar conclusion with the work of Danneville et al [7] in III-V field-effect transistors (FETs), namely, the noise sources in the device channel mostly originated from the source side.…”

On noise properties of transistors and amplifiers a critical review

“…Similar arguments can be made in reference to the so called "gate induced noise" which is to represent the noise imposed on the gate by channel carriers due to capacitve coupling (see for example the recent review papers on the modeling of noise in CMOS [14], [19], [20]). In a circuit model the postulated "gate induced noise" cannot be distinguished from the noise generated by the intrinsic gate resistance (see Fig.…”

“…Finally, in many CMOS modeling papers (for example [14], [19], [2 0]) an attempt is made to assess relative contributions to the total minimum noise temperature (noise figure) of different noise mechanisms. Typically, the contribution of gate noise is assessed at much less than 50 percent [\4], [\9], [20].…”

Investigation of Thermal Noise Factor in Nanoscale MOSFETs

“…It is 1 at V DS = 0 V and it converges into 2/3 at the saturation bias region. It has been widely known that the long-channel thermal noise model severely underestimates the shortchannel thermal noise due to short channel effects such as channel length modulation (CLM), velocity saturation effect (VSE), and carrier heating effect (CHE) [3][4][5][6][7][8][9][10]12]. As the channel length shrinks down to the nanoscale, these short-channel effects become more prominent in noise behaviors [13].…”

“…Since low noise design is one of the key issues in the overall analog and RF CMOS circuits, modeling of the noise characteristics of the nanoscale MOSFETs is important [1][2][3]. The channel thermal noise is the most dominant noise source of the MOSFETs at highfrequency [4][5][6][7].…”