MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

Lee, C.H.; Kim, Y.H.; Luan, H.F.; Lee, S.J.; Jeon, T.S.; Bai, Weiping; Kwong, D. L.

doi:10.1109/vlsit.2001.934987

Cited by 7 publications

(3 citation statements)

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“…Each component , where designates the band, is calculated separately for unbound states and bound states. For unbound states in the conduction band (5) and for unbound states in the valence band (6) where and Fermi-Dirac distribution functions for the gate and silicon substrate, respectively; lowest (highest) unbound state in the conduction (valence) band; charge of electron. While for bound states (7) where is approximated by the surface impact frequency for a two-dimensional (2-D) subband [21] ( 8) with the action integral between the classical turning points (9) and (10) where the contour integral is around the quantum well formed in the channel;…”

Section: Modelingmentioning

confidence: 99%

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Fan

Nieh

Lee

et al. 2002

IEEE Trans. Electron Devices

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Based on the energy-dispersion relation in each region of the gate-dielectric-silicon system, a tunneling model is developed to understand the gate current as a function of voltage and temperature. The gate capacitance is self-consistently calculated from Schrödinger and Poisson equations subject to the Fermi-Dirac statistics, using the same band structure in the silicon as used for tunneling injection. Franz two-band dispersion is assumed in the dielectric bandgap. Using a Wentzel-Kramer-Brillouin (WKB)-based approach, direct and Fowler-Nordheim (FN) tunneling and thermionic emission are considered simultaneously. The model is implemented for both the silicon conduction and valence bands and both gate-and substrate-injected currents. ZrO 2 NMOSFETs were studied through temperature-dependent -and -simulations. The extracted band gaps and band offsets of the ZrO 2 -and interfacial-Zr-silicate-layer are found to be comparable with the reported values. The gate currents in ZrO 2 -NMOSCAPs are found to be primarily contributed from the silicon conduction band and tunneling appears to be the most probable primary mechanism through the dielectric. Oscillations of gate currents and kinks of gate capacitance were observed near flat-band in the experiments. These phenomena might be caused by the interface states.Index Terms-High-K gate dielectric, leakage currents, MIS devices, MOSFETs, semiconductor device modeling, tunneling.

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Section: Modelingmentioning

confidence: 99%

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Fan

Nieh

Lee

et al. 2002

IEEE Trans. Electron Devices

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“…The recent introduction of metal gate enables us to consider ZrO 2 as an alternate high-k oxide again [5]. Previous researches showed higher leakage current density in ZrO 2 than in HfO 2 [6], [7], and smaller grain size in ZrO 2 or ZrHfO than in HfO 2 dielectric [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂

Cho

Kaczer

Kauerauf

et al. 2013

IEEE Electron Device Lett.

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The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO 2 and HfO 2 dielectrics with metal gate is investigated. The threshold voltage shift ( V TH ) at identical NBTI overdrive stress conditions is observed to be lower in ZrO 2 than in HfO 2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation ( N it ) in the sub-1-nanometer EOT devices, with ZrO 2 devices showing about one order of magnitude lower N it than HfO 2 device. However, the N it contribution to the total V TH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO 2 , which decisively reduces NBTI in ZrO 2 gate dielectric.Index Terms-Dielectric reliability, negative bias temperature instability (NBTI), oxide defect, thin equivalent oxide thickness (EOT).

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“…For many good reasons, HfO has been considered as one of the most promising high-K candidates [3]- [6]. For metal gate electrodes, TaN has been studied with high-K gate dielectrics, and superior thermal stability and electrical characteristics have been reported [7], [8]. These results suggest that TaN/HfO gate stack may be a promising candidate for future CMOS devices.…”

Section: Introductionmentioning

confidence: 99%

TDDB and Polarity-Dependent Reliability of High-Quality, Ultrathin CVD>tex<$hbox HfO_2$>/tex<Gate Stack With TaN Gate Electrode

Lee

Kwong

2004

IEEE Electron Device Lett.

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In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT = 8 5-10 5 A. It is found that, due to the asymmetric band structure of HfO 2 gate stack with an interfacial layer, the HfO 2 gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown ( BD ) is observed when BD is plotted as a function of gate voltage.The 10-year lifetime of an HfO 2 gate stack is projected to be = 1 63V for the equivalent oxide thickness (EOT) = 8 6 A and = 1 88 V for EOT = 10 6 A at 25 C. These excellent reliability characteristics are attributed to reduced leakage current of HfO 2 gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO 2 for the same EOT. However, at 150 C, and with area scaling to 0.1 cm 2 and low percentile of 0.01%, the maximum allowed voltages are projected to = 0 6 V and 0 75 V for EOT of 8.6, and 10.6 A, respectively.Index Terms-Hafnium oxide, high-K gate stack, metal gate electrode, reliability.

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MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

Cited by 7 publications

References 0 publications

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂

TDDB and Polarity-Dependent Reliability of High-Quality, Ultrathin CVD>tex<$hbox HfO_2$>/tex<Gate Stack With TaN Gate Electrode

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MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

Cited by 7 publications

References 0 publications

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Improved NBTI reliability with sub-1-nanometer EOT ZrO2 gate dielectric compared with HfO2

TDDB and Polarity-Dependent Reliability of High-Quality, Ultrathin CVD&gt;tex&lt;$hbox HfO_2$&gt;/tex&lt;Gate Stack With TaN Gate Electrode

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Product

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Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂

TDDB and Polarity-Dependent Reliability of High-Quality, Ultrathin CVD>tex<$hbox HfO_2$>/tex<Gate Stack With TaN Gate Electrode