Improved NBTI reliability with sub-1-nanometer EOT ZrO₂ gate dielectric compared with HfO₂

Abstract

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO 2 and HfO 2 dielectrics with metal gate is investigated. The threshold voltage shift ( V TH ) at identical NBTI overdrive stress conditions is observed to be lower in ZrO 2 than in HfO 2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation ( N it ) in the sub-1-nanometer EOT devices, with ZrO 2 devices showing about one order of magnitude lower N it than HfO 2 device. However, the N it contribution to the total V TH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO 2 , which decisively reduces NBTI in ZrO 2 gate dielectric.Index Terms-Dielectric reliability, negative bias temperature instability (NBTI), oxide defect, thin equivalent oxide thickness (EOT).

Improved Electrical Characteristics of Ge pMOSFETs With ZrO2/HfO2Stack Gate Dielectric

“…The peak hole mobility are 320 and 283 cm 2 /V-sec for devices with HfO 2 and ZrO 2 gate dielectrics, respectively. The low peak hole mobility of ZrO 2 device can be explained by the intrinsically high interface charge density, which greatly induces the remote Coulomb scattering [16]. However, the hole mobility of ZrO 2 /HfO 2 device is ∼335 cm 2 /V-sec, which is enhanced ∼18% over that of others.…”

Investigation of abnormal negative threshold voltage shift under positive bias stress in input/output n-channel metal-oxide-semiconductor field-effect transistors with TiN/HfO2 structure using fast I-V measurement

“…This is because channel electrons inject into high-k bulk traps, as shown in previous letters. 30,31 Fig. 5(b) shows a comparison of DV t,hysteresis À (t rising time ¼ t falling time ) for different devices with a constant electric field (V base level ¼ V FB À E 1 EOT, V high level ¼ V FB þ w s þ E 2 EOT).…”

High Dielectric Constant Materials for Nanoscale Devices and Beyond

“…48,49 However, the negative bias temperature instability (NBTI) for p-channel MOSFETs and positive bias temperature instability (PBTI) for n-channel MOSFETs remain as serious degradation mechanisms when device temperature is increased.…”

“…Since the introduction of HfO 2 in mainstream technology 1 its reliability has been extensively studied under different stress conditions. 48,49 However, the negative bias temperature instability (NBTI) for p-channel MOSFETs and positive bias temperature instability (PBTI) for n-channel MOSFETs remain as serious degradation mechanisms when device temperature is increased. 1 Interface state defect generation triggered by Si-H bond breaking at the interface is a point of major concern.…”