Monolithic integration of low-pass filters with ESD protections on p + silicon/porous silicon substrates

Capelle, Marie; Billoue, Jérôme; Concord, J.; Poveda, Patrick; Gautier, Gaël

doi:10.1016/j.sse.2015.11.026

Cited by 10 publications

(3 citation statements)

References 10 publications

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“…These prototypes were composed of common mode filters and protection diodes against electrostatic discharges. The relevance of PSi implementation was validated for low-pass filters (9). The same masking layer was also successfully used during the etching of PSi TRIAC peripheries (see last part) (7).…”

Section: New Challenges In Rf Devices Integrating Psimentioning

confidence: 99%

(Invited) Recent Advances in Porous Silicon Based Microelectronic Devices

Gautier¹,

Billoue²,

Defforge³

et al. 2018

ECS Trans.

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In this paper, we show some recent advances that have been performed in the field of Porous Silicon (PSi) applied to microelectronic devices. Indeed, many components can implement the specific properties of this nanostructured material. Therefore, it has been identified as a serious candidate for the integration of complex functions in a single silicon wafer in a "more than Moore" context. In particular, it will be shown that PSi etching is nowadays mastered at a wafer scale on localized areas, 3D surfaces or on the backside of devices. Some typical examples of applications such as RF devices, AC power switches or ultrasonic transducers will be described in order to illustrate the benefits PSi technology can provide.

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Section: New Challenges In Rf Devices Integrating Psimentioning

confidence: 99%

(Invited) Recent Advances in Porous Silicon Based Microelectronic Devices

Gautier¹,

Billoue²,

Defforge³

et al. 2018

ECS Trans.

View full text Add to dashboard Cite

show abstract

“…Semiconductor materials based filters have attracted more and more researchers' attention, many outstanding works such as on silicon [5,6] (Si), silicon germanium [7,8] (SiGe), gallium arsenide [9] (GaAs), and other advanced semiconductor materials [10] are proposed. However, with the rapid developing of the wireless communication systems, the first and second generation semiconductors are getting to be hard to satisfying the demand of the frequency and power.…”

Section: Introductionmentioning

confidence: 99%

Terahertz monolithic integrated narrow-band filter based on the silicon carbide substrate

Liu¹,

Yang²,

Li³

et al. 2023

Semicond. Sci. Technol.

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This paper presented a narrow-band terahertz integrated cavity filter based on the silicon carbide (SiC) substrate. By introducing two metalized via-holes in a rectangular integrated cavity, an integrated coupling cavity was built, on the one hand, to operate as a coupling structure; on the other hand, to control the direct coupling between input and output feeding lines, further to control the frequency of the transmission zero. This novel approach was thoroughly investigated with attention paid to the position of the via-holes. Based on this approach, a terahertz narrow-band filter was realized on the semi-insulating SiC substrate, demonstrated good filtering performance, especially the stopband rejection characteristic, and established the groundwork for the production of the terahertz monolithic integrated circuit (TMIC).

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“…This solution aimed to provide solution to reduce the cost and the fabrication process complexity. Thanks to its large surface area and the control of its layer properties through various characterizations, most of the works related to PSi as substrate have been devoted to different applications such as electronic, 7 photonic crystal sensors, 8 and magnetic sensing. 9 However, the compatibility of the PSi with industrial processes remains questionable, and the study of its mechanical characteristics should be performed while accounting this issue.…”

Section: Introductionmentioning

confidence: 99%

Structural and nanomechanical properties of porous silicon: Cheap substrate for CMOS process industry

Belaroussi

Scheen

Saadi³

et al. 2020

Surface & Interface Analysis

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The surface topology of porous silicon (PSi) is a relevant parameter that decides the compatibility of such substrate with CMOS process. Using standard resistivity (1–10 Ω·cm) of Si substrate to fabricate PSi‐S is a low cost solution for the industry. In this paper, through an atomic force microscopy (AFM) analysis, the root mean square (RMS) roughness, the power spectral density and the correlation length were determined for different PSi layers. Furthermore, the measured hardness, Young's modulus, and stress have been made for different thicknesses of PSi: 5, 10, 50, and 200 μm. The obtained results demonstrated that very interesting properties have been achieved with the 50 μm‐thick PSi‐S layer with a maximum porosity around 65%, a surface roughness less than 1 nm and a hardness value of (~1 GPa). The realized results encourage the utilization the PSi‐based substrate into the industry process and thus the development of a Systems‐on‐Chip (SoC).

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Monolithic integration of low-pass filters with ESD protections on p + silicon/porous silicon substrates

Cited by 10 publications

References 10 publications

(Invited) Recent Advances in Porous Silicon Based Microelectronic Devices

(Invited) Recent Advances in Porous Silicon Based Microelectronic Devices

Terahertz monolithic integrated narrow-band filter based on the silicon carbide substrate

Structural and nanomechanical properties of porous silicon: Cheap substrate for CMOS process industry

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