Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory

Dutta, Sourav; Ye, H.; Chakraborty, Wriddhi; Luo, Yuan-Chun; Jose, Matthew San; Grisafe, Benjamin; Khanna, Abhishek; Lightcap, Ian V.; Shindé, Subhash L.; Yu, Shimeng; Datta, Suman

doi:10.1109/iedm13553.2020.9371974

Cited by 72 publications

(36 citation statements)

References 2 publications

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“…The advantage of HZO over other perovskite ferroelectric materials and Sidoped hafnium oxides (HSO) has been mentioned in previous reports, which involves ease of deposition by the ALD process, scalability to thin film, and lower process temperature (Muller et al, 2012;Jerry et al, 2017;Kim H. et al, 2018;Ali et al, 2019;Ni et al, 2019;Cheema et al, 2020). Recent reports have also shown that low process temperature, superior interface quality, and reducing the numbers of defect sites in HZO improve the endurance of the HZO-based transistors (Dutta et al, 2020;De et al, 2021a;De et al, 2021b;Khakimov et al, 2021). Apart from the device structure, low process temperature and interface properties, the pulse scheme, and bias-technique during the WRITE operation also play an important role in determining the WRITE-endurance limit of the device.…”

Section: Introductionmentioning

confidence: 99%

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Baig

Qiu

et al. 2022

Front. Nanotechnol.

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This work presents 2-bits/cell operation in deeply scaled ferroelectric finFETs (Fe-finFET) with a 1 µs write pulse of maximum ±5 V amplitude and WRITE endurance above 109 cycles. Fe-finFET devices with single and multiple fins have been fabricated on an SOI wafer using a gate first process, with gate lengths down to 70 nm and fin width 20 nm. Extrapolated retention above 10 years also ensures stable inference operation for 10 years without any need for re-training. Statistical modeling of device-to-device and cycle-to-cycle variation is performed based on measured data and applied to neural network simulations using the CIMulator software platform. Stochastic device-to-device variation is mainly compensated during online training and has virtually no impact on training accuracy. On the other hand, stochastic cycle-to-cycle threshold voltage variation up to 400 mV can be tolerated for MNIST handwritten digits recognition. A substantial inference accuracy drop with systematic retention degradation was observed in analog neural networks. However, quaternary neural networks (QNNs) and binary neural networks (BNNs) with Fe-finFETs as synaptic devices demonstrated excellent immunity toward the cumulative impact of stochastic and systematic variations.

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Section: Introductionmentioning

confidence: 99%

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Baig

Qiu

et al. 2022

Front. Nanotechnol.

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“…Harnessing the polar orthorhombic phase Pca21 in thin films of doped Hafnium Oxide (HfO2), one can construct a one transistor non-volatile ferroelectric memory (FeFET) that can serve as a logiccompatible, high-performance embedded non-volatile memory [2]. Recent demonstrations of robust memory operation in FeFETs with high density integration in relatively scaled CMOS technology nodes (28nm planar bulk [4] and 22nm FD-SOI [5]) has provided legitimacy of FeFET as a contender for eNVM with best-in-class energy efficiency, latency and footprint area for CIM applications standing next to spin-transfer-torque magnetic random-access memory (STT-MRAM), resistive random-access memory (RRAM) and phase change memory (PCM) [2], [6]- [8]. However, FeFETs still face several key roadblocks such as logic-compatible programming, write endurance, read-after-write latency and BEOL-compatible low temperature processing [9]- [13] for integration in the BEOL.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, improving the write endurance of FeFET requires us to either re-explore the known techniques of IL engineering in HKMG technology such as reducing the IL thickness through scavenging [16] and increasing the dielectric constant of IL [17], or re-imagine novel ways to build an IL-free FeFET with high write endurance. The latter can be achieved by fabricating a back-gated, channel-last FeFET where an oxide semiconductor channel is grown directly on top of the ferroelectric HZO gate oxide, analogous to the fabrication of thin-film transistors (TFTs) used commercially in flat-panel display application [8], [18]- [22]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Logic Compatible High-Performance Ferroelectric Transistor Memory

Dutta

Aabrar

et al. 2022

IEEE Electron Device Lett.

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Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric gate stack and silicon channel suffers from high write voltage, limited write endurance and large read-after-write latency due to early IL breakdown and charge trapping and detrapping at the interface. We demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricate IL-free FeFETs with 28nm channel length and 126nm width under a thermal budget <400 0 C by integrating 5nm thick Hf0.5Zr0.5O2 gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report 1.2V memory window and read current window of 10 5 for program and erase, write latency of 20ns with ±2V write pulses, read-after-write latency <200ns, write endurance cycles exceeding 5x10 10 and 2-bit/cell programming capability. Array-level analysis establishes IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance on-chip buffer memory and multi-bit weight cell for compute-in-memory accelerators.

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“…Compute-in-memory (CIM) is a promising solution to alleviate the memory access bottleneck and has achieved attractive energy efficiency when implemented with mature SRAM technology at 7 nm ( Dong et al, 2020 ). With recent progress in emerging nonvolatile memory (eNVM) devices such as resistive random access memory (RRAM) ( Xue et al, 2020 ), phase change memory (PCM) ( Burr et al, 2015 ), and ferroelectric field-effect transistor (FeFET) ( Dutta et al, 2020 ), the application of a CIM-based DNN accelerator is even more intriguing since eNVMs offer low leakage power and nonvolatility which are necessary for dynamic power gating and instant on and off operations in smart edge devices.…”

Section: Introductionmentioning

confidence: 99%

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Peng

et al. 2021

Front. Artif. Intell.

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Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardware accelerators. DNN+NeuroSim is an integrated benchmark framework supporting flexible and hierarchical CIM array design options from a device level, to a circuit level and up to an algorithm level. In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations. First, the parameters of a memory device and CMOS transistor are extracted from the foundry’s process design kit (PDK) and employed in the NeuroSim settings; the peripheral modules and operating dataflow are also configured to be the same as the actual chip implementation. Next, the area, critical path, and energy consumption values from the SPICE simulations at the module level are compared with those from NeuroSim. Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc. We show that the prediction from NeuroSim is precise with chip-level error under 1% after the calibration. Finally, the system-level performance benchmark is conducted with various device technologies and compared with the results before the validation. The general conclusions stay the same after the validation, but the performance degrades slightly due to the post-layout calibration.

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Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory

Cited by 72 publications

References 2 publications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Logic Compatible High-Performance Ferroelectric Transistor Memory

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

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