Logic Compatible High-Performance Ferroelectric Transistor Memory

Abstract

Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric gate stack and silicon channel suffers from high write voltage, limited write endurance and large read-after-write latency due to early IL breakdown and charge trapping and detrapping at the interface. We demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricate IL-free FeFETs with 28nm channel length and 126nm width under a thermal budget <400 0 C by integrating 5nm thick Hf0.5Zr0.5O2 gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report 1.2V memory window and read current window of 10 5 for program and erase, write latency of 20ns with ±2V write pulses, read-after-write latency <200ns, write endurance cycles exceeding 5x10 10 and 2-bit/cell programming capability. Array-level analysis establishes IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance on-chip buffer memory and multi-bit weight cell for compute-in-memory accelerators.

READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine Applications

“…All four terminals (gate, drain, source, and bulk) were held at 0V during this time. Although recent studies have shown much lower latency between WRITE and READ operations [31,32], this value has been optimized for the array-level operations with 28nm HKMG FeFETs (n-type) in 300mm wafers [33]. The pulse applied at the gate terminal during the WRITE operations aligns the ferroelectric dipoles according to their polarity, affecting the surface charge density of the channel, conductance of the channel (Gch), and the threshold voltage (Vth).…”

Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures

“…The presence of holes in the channel degrades the endurance most significantly as we have shown recently. 29 On the other hand, back end of the line (BEOL) FEFETs with non-Si channel such as with In 2 O 3 channel, operating in depletion 14 or fully depleted FEFETs, 30 have much higher endurance. In other words, complete assessment of endurance properties needs to be performed in FEFET structures with scavenged oxides (not in FE MOS capacitors).…”

“…Reducing the thickness of the IL or eliminating it altogether has been suggested as one of the key strategies to reduce the write voltage in FEFETs. 5,14,15 Techniques to reduce the IL thickness, often referred to as oxygen scavenging, were investigated in the context of the high-k-metal-gate technology development for standard complementary metal−oxide−semiconductor (CMOS) transistors, to reduce the effective oxide thickness (EOT) and improve the on-current. 16−18 Previous studies on amorphous dielectric (DE) HfO 2 gate oxides have successfully demonstrated significant EOT reduction by employing remote scavenging (sometimes called gettering) metal electrodes for SiO 2 IL scavenging.…”

“…Due to the low dielectric constant (∼4) of the SiO 2 interfacial layer (IL), there is a large drop in the gate voltage across the IL which increases the write voltage to a value much higher than the coercive voltage of the equivalent, stand-alone ferroelectric layer. Reducing the thickness of the IL or eliminating it altogether has been suggested as one of the key strategies to reduce the write voltage in FEFETs. ,, …”

“…In this study, a remote scavenging electrode of Ti was employed with a thin 2 nm TiN capping layer to study the effects of IL scavenging in ferroelectric metal–oxide–semiconductor (FE-MOS) capacitor structures. The prototype ferroelectric devices using HZO on highly doped Si has been reported previously. , When compared with MOS devices with conventional thick TiN electrodes, the remote scavenging electrode devices show a significant reduction in IL thickness resulting in a lower switching voltage and a 2× increase in remnant polarization ( P r ) compared to a conventional device. These results are consistent with DFT modeling showing that the interlayer screens the electric field from the ferroelectric thereby decreases the field inside the semiconductor electrode and increases the voltage required for switching.…”