NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Lu, Anni; Peng, Xiaochen; Li, Wan–Tong; Jiang, Hongwu; Yu, Shimeng

doi:10.3389/frai.2021.659060

Cited by 27 publications

(12 citation statements)

References 20 publications

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“…To estimate the latency of the delay lines, and TDC (collectively referred to accumulation & sample stage), SPICE simulation with the cryogenic CMOS model was employed. For the estimation of following peripheral circuitry including shift-and-add, etc., NeuroSim [12] incorporated with the cryogenic CMOS model was used. Fig.…”

Section: A Benchmark Models and D = 3 Simulation Resultsmentioning

confidence: 99%

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter

Kang

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Abstract-This paper explores a compute-in-memory (CIM) paradigm's new application for cryogenic neural network. Using the 28 nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of 1) area-efficient unit delay cell design for cryogenic operation and 2) area and power efficient, and high-resolution achievable successive approximation register (SAR) time-digital converter (TDC) is proposed. The benchmark simulation first shows that the proposed macro has better latency than the current-based compute-in-memory counterpart. Next, the simulation further shows that it has better scalability for larger size decoder design and process technology optimization.

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Section: A Benchmark Models and D = 3 Simulation Resultsmentioning

confidence: 99%

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter

Kang

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Our profile tool is very simple and restricted (narrowed to our architecture). One of the well-developed profilers for the CIM hardware accelerator is NeuroSim [ 32 ]. However, the reason why we do not use the existing profiling tool is that our architecture design focus is on CIM macro development.…”

Section: Discussionmentioning

confidence: 99%

SRAM-Based CIM Architecture Design for Event Detection

Sulaiman¹,

Lin²,

Li³

et al. 2022

Sensors

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Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the high computational complexity and high-energy consumption of CNNs trammel their application in hardware accelerators. Computing-in-memory (CIM) is the technique of running calculations entirely in memory (in our design, we use SRAM). CIM architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. CIM-based architecture for event detection is designed to trigger the next stage of precision inference. To implement an SRAM-based CIM accelerator, a software and hardware co-design approach must consider the CIM macro’s hardware limitations to map the weight onto the AI edge devices. In this paper, we designed a hierarchical AI architecture to optimize the end-to-end system power in the AIoT application. In the experiment, the CIM-aware algorithm with 4-bit activation and 8-bit weight is examined on hand gesture and CIFAR-10 datasets, and determined to have 99.70% and 70.58% accuracy, respectively. A profiling tool to analyze the proposed design is also developed to measure how efficient our architecture design is. The proposed design system utilizes the operating frequency of 100 MHz, hand gesture and CIFAR-10 as the datasets, and nine CNNs and one FC layer as its network, resulting in a frame rate of 662 FPS, 37.6% processing unit utilization, and a power consumption of 0.853 mW.

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“…We have performed a system-level simulation of handwritten digit recognition from the data set of "Modified National Institute of Standards and Technology (MNIST)" to quantify the efficacy of current limited FeFET-based crossbar array in multi-layer perceptron (MLP) based NNs as synaptic cores [24], [25]. Experimentally obtained device-to-device variation and retention degradation of I BL have been modeled for NN simulation.…”

Section: Applications To In-memory-computingmentioning

confidence: 99%

28 nm HKMG-Based Current Limited FeFET Crossbar-Array for Inference Application

Müller

Thunder

et al. 2022

IEEE Trans. Electron Devices

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This article reports a novel ferroelectric fieldeffect transistor (FeFET)-based crossbar array cascaded with an external resistor. The external resistor is shunted with the column of the FeFET array, as a current limiter and reduces the impact of variations in drain current (I d ), especially in a low threshold voltage (LVT) state. We have designed crossbar arrays of 8 × 8 sizes and performed multiply-and-accumulate (MAC) operations. Furthermore, we have evaluated the performance of the current limited FeFET crossbar array in system-level applications. Finally, the system-level performance evaluation was done by neuromorphic simulation of the resistor-shunted FeFET crossbar array. The crossbar array achieved software-comparable inference accuracy (∼97%) for National Institute of Standards and Technology (MNIST) datasets with multilayer perceptron (MLP) neural network, whereas the crossbar arrays built solely with FeFETs failed to learn, yielding only 9.8% accuracy.

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NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Cited by 27 publications

References 20 publications

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter

SRAM-Based CIM Architecture Design for Event Detection

28 nm HKMG-Based Current Limited FeFET Crossbar-Array for Inference Application

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