28 nm HKMG-Based Current Limited FeFET Crossbar-Array for Inference Application

Abstract

This article reports a novel ferroelectric fieldeffect transistor (FeFET)-based crossbar array cascaded with an external resistor. The external resistor is shunted with the column of the FeFET array, as a current limiter and reduces the impact of variations in drain current (I d ), especially in a low threshold voltage (LVT) state. We have designed crossbar arrays of 8 × 8 sizes and performed multiply-and-accumulate (MAC) operations. Furthermore, we have evaluated the performance of the current limited FeFET crossbar array in system-level applications. Finally, the system-level performance evaluation was done by neuromorphic simulation of the resistor-shunted FeFET crossbar array. The crossbar array achieved software-comparable inference accuracy (∼97%) for National Institute of Standards and Technology (MNIST) datasets with multilayer perceptron (MLP) neural network, whereas the crossbar arrays built solely with FeFETs failed to learn, yielding only 9.8% accuracy.

Ferroelectric Content-Addressable Memory Cells with IGZO Channel: Impact of Retention Degradation on the Multibit Operation

“…This cascoded transistor connected on top of the FeTFT reduces the impact of device variation, especially in the ON-state current. The details of this 1F-1T structure and their applications in memory arrays have been described before. ,, In this work, we primarily focus on the impact of retention degradation. Figure b shows a 1 × 4 CAM array, which is constructed by connecting 4 CAM cells on the same match line.…”

“…The details of this 1F-1T structure and their applications in memory arrays have been described before. 40 , 46 , 47 In this work, we primarily focus on the impact of retention degradation. Figure 2 b shows a 1 × 4 CAM array, which is constructed by connecting 4 CAM cells on the same match line.…”

Design of Variation-Tolerant 1F-1T Memory Array for Neuromorphic Computing

“…Since the variations mostly affect the LVT state, we can easily address the issue by limiting the ON current. The logic transistor acts as a current limiter like the resistive element demonstrated in our previous works [13]. Figure .5a shows the transfer characteristics of the proposed devices with the same pulsing scheme as a single FeFET cell.…”

“…The basic step of IMC is vector-matrix multiplication (VMM). Many eNVMs such as resistive random access memory (ReRAM) [5]- [7], phase change memory (PCM) [8], [9], and FeFETs [10]- [13] have been investigated in recent years.…”

“…Fig. (1) (a) Schematic and (b) TEM image of a 28nm HKMG-based FeFET fabricated at GolbalFoundries [12],[13]. The experiment began with fabricating the crossbar arrays and memory cell structures on 300mm wafers using the 28nm HKMG technology at GlobalFoundries.Figure.1a shows the schematic of a HKMG FeFET, and Figure.1b shows the transmission electron microscopic (TEM) image.…”