Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter

Abstract

Abstract-This paper explores a compute-in-memory (CIM) paradigm's new application for cryogenic neural network. Using the 28 nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of 1) area-efficient unit delay cell design for cryogenic operation and 2) area and power efficient, and high-resolution achievable successive approximation register (SAR) time-digital converter (TDC) is proposed. The benchmark simulation first shows that the proposed macro has better latency than the current-based compute-in-memory counterpart. Next, the simulation further shows that it has better scalability for larger size decoder design and process technology optimization.

A 115.1 TOPS/W, 12.1 TOPS/mm2 Computation-in-Memory using Ring-Oscillator based ADC for Edge AI

“…Recent works on ADC designs can be classified into three classes based on their intermediate physical quantity used for conversion: 1) voltage (V-ADC), 2) current (C-ADC), and 3) time-based ADCs (T-ADC). V-ADCs and T-ADCs are expensive as they typically consist of large components such as large hold capacitors [4,[6][7][8][9][10] or/and a series of sense amplifiers [4,[7][8][9] and large time-digital converters (TDCs) [10,11], respectively, along with digital-to-analog converters (DACs) [8,[10][11][12][13] for providing reference signals to compute intermediate output calculations. In addition, these ADC classes require several power-hungry comparison cycles for their final digital output conversions.…”