Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Abstract

This work presents 2-bits/cell operation in deeply scaled ferroelectric finFETs (Fe-finFET) with a 1 µs write pulse of maximum ±5 V amplitude and WRITE endurance above 109 cycles. Fe-finFET devices with single and multiple fins have been fabricated on an SOI wafer using a gate first process, with gate lengths down to 70 nm and fin width 20 nm. Extrapolated retention above 10 years also ensures stable inference operation for 10 years without any need for re-training. Statistical modeling of device-to-device and cycle-to-cycle variation is performed based on measured data and applied to neural network simulations using the CIMulator software platform. Stochastic device-to-device variation is mainly compensated during online training and has virtually no impact on training accuracy. On the other hand, stochastic cycle-to-cycle threshold voltage variation up to 400 mV can be tolerated for MNIST handwritten digits recognition. A substantial inference accuracy drop with systematic retention degradation was observed in analog neural networks. However, quaternary neural networks (QNNs) and binary neural networks (BNNs) with Fe-finFETs as synaptic devices demonstrated excellent immunity toward the cumulative impact of stochastic and systematic variations.

Gate-Stack Engineered IGZO-based Multi-bit OTP FeTFT with Lifelong Retention for Inference Engine Applications

“…The retention characteristics (Figure. [4,6,8]. However, while the tHZO was greater than 3tIGZO, the erase was possible by applying a negative voltage pulse at the gate terminal, which agrees with the results obtained for the MFSM structure.…”

“…Finally, the system level validation of the inference engine was performed using the CIMulator platform [4]. The neural network architecture was like the one described in our previous work [4], which comprises an MLP with three layers.…”

“…based FeFETs [1][2][3], FefinFETs [4][5][6], and FeTFTs [7,8] have paved the way for further scaling and monolithic 3D integration with thin-film transistors (TFTs). However, the TFTs with polycrystalline silicon channels suffer from retention degradation, high thermal budget, and mobility (µ) degradation [9].…”

“…However, the TFTs with polycrystalline silicon channels suffer from retention degradation, high thermal budget, and mobility (µ) degradation [9]. The device variation and endurance-retention tradeoff play a pivotal role in the performance of the synaptic core of neural networks [4,10]. The WRITE endurance directly influences the device's ability to be deployed in online training, whereas retention is essential to carry out the inference operation without re-programming.…”

“…The WRITE endurance directly influences the device's ability to be deployed in online training, whereas retention is essential to carry out the inference operation without re-programming. Although online training is more noise-tolerant, it requires very high endurance, which may exceed the limit of the synaptic devices (>10 10 cycles) [4]. Therefore, it is pragmatic to carry out the neural network training offline and run the inference in the hardware.…”