Modular multi-ported SRAM-based memories

Abstract

Multi-ported RAMs are essential for high-performance parallel computation systems. VLIW and vector processors, CGRAs, DSPs, CMPs and other processing systems often rely upon multi-ported memories for parallel access, hence higher performance. Although memories with a large number of read and write ports are important, their high implementation cost means they are used sparingly in designs. As a result, FPGA vendors only provide dual-ported block RAMs to handle the majority of usage patterns. In this paper, a novel and modular approach is proposed to construct multi-ported memories out of basic dual-ported RAM blocks. Like other multi-ported RAM designs, each write port uses a different RAM bank and each read port uses bank replication. The main contribution of this work is an optimization that merges the previous live-value-table (LVT) and XOR approaches into a common design that uses a generalized, simpler structure we call an invalidation-based live-value-table (I-LVT). Like a regular LVT, the I-LVT determines the correct bank to read from, but it differs in how updates to the table are made; the LVT approach requires multiple write ports, often leading to an areaintensive register-based implementation, while the XOR approach uses wider memories to accommodate the XOR-ed data and suffers from lower clock speeds. Two specific I-LVT implementations are proposed and evaluated, binary and one-hot coding. The I-LVT approach is especially suitable for larger multi-ported RAMs because the table is implemented only in SRAM cells. The I-LVT method gives higher performance while occupying less block RAMs than earlier approaches: for several configurations, the suggested method reduces the block RAM usage by over 44% and improves clock speed by over 76%. To assist others, we are releasing our fully parameterized Verilog implementation as an open source hardware library. The library has been extensively tested using ModelSim and Altera's Quartus tools.

Modular SRAM-Based Binary Content-Addressable Memories

“…To fit some applications that require single-cycle writing, e.g. caches and TLBs, the proposed technique can be enhanced to support single cycle write by using multi-write RAM [18].…”

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip

“…Then, we analyze all data structures following the same descending order and we seek for opportunities to reuse the banks. In particular, when a data structure requires a lower number of parallel blocks, it can reuse the exceeding ones in series to virtually increase the capacity of the parallel blocks (lines [11][12][13][14][15][16][17]. We also check if the data structure can fit into this new configuration (line 12).…”

“…Abdelhadi and Lemieux [14] analyzed various techniques to perform multiple memory operations in the same clock cycle. Among these, raising the memory frequency is usually limited by the technology, while bank arbitration affects the accelerator performance.…”

“…Additionally, while processor memories are designed for sequential access (even in case of memory sharing with the accelerator [12], [13]), PLMs require multiple ports to allow the accelerator logic to perform multiple memory operations within the same clock cycle and increase the hardware parallelism. There are different solutions to implement multiport memories [14]. Distributed registers, which are completely contained into the accelerator logic, are used for small and frequently accessed data structures.…”

Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems

“…If any processor cannot match the rate of notifications, then the L2 Arbiter must stall until the notifications are handled, harming system throughput. Multipumping [5] is one of several techniques used to effectively double the number of ports on the memory [1], which we use to allow our system to double the number of reads and/or writes that can be executed per cycle. Multi-pumping allows us to integrate invalidation look-ups without impacting the normal operation of the cache.…”