Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems

Matthews, Eric; Doyle, Nicholas C.; Shannon, Lesley

doi:10.1145/2684746.2689083

Cited by 16 publications

(7 citation statements)

References 11 publications

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“…Recent work has also explored the design space of the cache micro-architecture [15][16][17][18][19]. Matthews et al [17] explore the efficiency in terms of speed-up versus area increase of parallel coherent L1 caches with respect to size, associativity and replacement rule in an FPGA-based soft multi-core processor.…”

Section: Related Workmentioning

confidence: 99%

“…Matthews et al [17] explore the efficiency in terms of speed-up versus area increase of parallel coherent L1 caches with respect to size, associativity and replacement rule in an FPGA-based soft multi-core processor. Similarly, Choi et al [18] compare different configurations of cache size, line size and associativity of shared on-chip caches, in addition to two approaches for increasing the number of access ports of the shared cache.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Custom Multicache Architectures for Heap Manipulating Programs

Winterstein

Fleming

Yang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an FPGA accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a common approach to address this problem and the optimization of the cache architecture introduces yet another complex design space. This paper presents a high-level synthesis (HLS) design aid that automatically generates parallel multi-cache systems which are tailored to the specific requirements of the application. Our program analysis identifies non-overlapping memory regions, supported by private caches, and regions which are shared by parallel units after parallelization, which are supported by coherent caches and synchronization primitives. It also decides whether the parallelization is legal with respect to data dependencies. The novelty of this work is the focus on programs using dynamically allocated, pointer-based data structures which, while common in software engineering, remain difficult to analyze and are beyond the scope of the overwhelming majority of HLS techniques to date. Secondly, we devise a high-level cache performance estimation to find a heterogeneous configuration of cache sizes that maximizes the performance of the multi-cache system subject to an on-chip memory resource constraint. We demonstrate our technique with three case studies of applications using dynamic data structures and use Xilinx Vivado HLS as an exemplary HLS tool. We show up to 15× speed-up after parallelization of the HLS implementations and the insertion of the application-specific distributed hybrid multi-cache architecture. ¶

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Custom Multicache Architectures for Heap Manipulating Programs

Winterstein

Fleming

Yang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Recent related work has also explored the design space of the cache micro-architecture [65,66,42] beyond inter-cache coherency. Matthews et al [65] explore the e ciency in terms of speed-up versus area increase of parallel coherent L1 caches with respect to size, associativity and replacement rule in an FPGA-based soft multi-core processor. Similarly,…”

Section: Profiling and User Annotation-based Approachesmentioning

confidence: 99%

Separation Logic for High-level Synthesis

Winterstein¹

2017

Springer Theses

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High-level synthesis (HLS) promises a significant shortening of the FPGA design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures and dynamic memory allocation remain difficult to implement well, yet such constructs are widely used in software. Automated optimizations that leverage the memory bandwidth of FPGAs by distributing the application data over separate banks of on-chip memory are often ineffective in the presence of dynamic data structures, due to the lack of an automated analysis of pointer-based memory accesses. In this work, we take a step towards closing this gap. We present a static analysis for pointer-manipulating programs which automatically splits heap-allocated data structures into disjoint, independent regions. The analysis leverages recent advances in separation logic, a theoretical framework for reasoning about heap-allocated data which has been successfully applied in recent software verification tools. Our algorithm focuses on dynamic data structures accessed in loops and is accompanied by automated source-to-source transformations which enable automatic loop parallelization and memory partitioning by off-the-shelf HLS tools. We demonstrate the successful loop parallelization and memory partitioning by our tool flow using three real-life applications which build, traverse, update and dispose dynamically allocated data structures. Our case studies, comparing the automatically parallelized to the direct HLS implementations, show an average latency reduction by a factor of 2× across our benchmarks.

show abstract

Section: Related Workmentioning

confidence: 99%

“…Recent work has also explored the design space of the cache micro-architecture [7], [19], [20]. Matthews et al [20] explore the efficiency in terms of speed-up versus area increase of parallel coherent L1 caches with respect to size, associativity and replacement rule in an FPGAbased soft multi-core processor. Similarly, Choi et al [19] compare different configurations of cache size, line size and associativity of shared on-chip caches, in addition to two approaches for increasing the number of access ports of the shared cache.…”

Section: Related Workmentioning

confidence: 99%

Custom-sized caches in application-specific memory hierarchies

Winterstein

Fleming

Yang

et al. 2015

2015 International Conference on Field Programmable Technology (FPT)

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Developing FPGA implementations with an input specification in a high-level programming language such as C/C++ or OpenCL allows for a substantially shortened design cycle compared to a design entry at register transfer level. This work targets high-level synthesis (HLS) implementations that process large amounts of data and therefore require access to an off-chip memory. We leverage the customizability of the FPGA on-chip memory to automatically construct a multi-cache architecture in order to enhance the performance of the interface between parallel functional units of the HLS core and an external memory. Our focus is on automatic cache sizing. Firstly, our technique determines and uses up unused left-over block RAM resources for the construction of on-chip caches. Secondly, we devise a high-level cache performance estimation based on the memory access trace of the program. We use this memory trace to find a heterogeneous configuration of cache sizes, tailored to the application's memory access characteristic, that maximizes the performance of the multi-cache system subject to an on-chip memory resource constraint. We evaluate our technique with three benchmark implementations on an FPGA board and obtain a reduction in execution latency of up to 2× (1.5× on average) when compared to a one-size-fits-all cache sizing. We also quantify the impact of our automatically generated cache system on the overall energy consumption of the implementation.

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Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems

Cited by 16 publications

References 11 publications

Custom Multicache Architectures for Heap Manipulating Programs

Custom Multicache Architectures for Heap Manipulating Programs

Separation Logic for High-level Synthesis

Custom-sized caches in application-specific memory hierarchies

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