Modeling TCAM power for next generation network devices

Agrawal, Banit; Sherwood, Timothy

doi:10.1109/ispass.2006.1620796

Cited by 99 publications

(64 citation statements)

References 15 publications

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“…Therefore, in our simulation, we include 20% power consumption for this fully associative cache. We also simulate TCAM's power consumption using a recent model [3]. All three schemes are simulated under 0.18µm technology.…”

Section: Experiments Resultsmentioning

confidence: 99%

Power Efficient IP Lookup with Supernode Caching

Peng

Duan

2007

IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference

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Abstract-In this paper, we propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. In stead of using an expensive TCAM based scheme, we implement a set associative SRAM based cache. We organize the IP routing table as a supernode tree (a tree bitmap structure) [5]. We add a small supernode cache in-between the processor and the low level memory containing the IP routing table in a tree structure. The supernode cache stores recently visited supernodes of the longest matched prefixes in the IP routing tree. A supernode hitting in the cache reduces the number of accesses to the low level memory, leading to a fast IP lookup. According to our simulations, up to 72% memory accesses can be avoided by a 128KB supernode cache for the selected three trace files. Average supernode cache miss ratio is as low as 4%. Compared to a TCAM with the same size, 77% of energy consumption can be reduced.

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Section: Experiments Resultsmentioning

confidence: 99%

Power Efficient IP Lookup with Supernode Caching

Peng

Duan

2007

IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference

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“…We simulated the design at the gate level to capture switching activity and used Synopsys Power Compiler [25] to calculate power consumption. For TCAM power and energy consumption we utilized a TCAM power estimator [1]. We used the Artisan memory compiler [4] to model the queue …”

Section: Methodsmentioning

confidence: 99%

“…One TCAM access consumes 177 mW of power [1] and read and write power of the queue is 45 mW and 49.5 mW respectively. TCAM power contributes heavily to overall power consumption because it is accessed nearly every cycle due to speculative searching.…”

Section: Power and Area Overheadmentioning

confidence: 99%

A One-Shot Configurable-Cache Tuner for Improved Energy and Performance

Gordon-Ross¹,

Viana²,

Vahid³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Third, TCAM chips consume lots of power. The power consumption of a TCAM chip is about 1.85 Watts per Mb [2]. This is roughly 30 times larger than a comparably sized SRAM chip [10].…”

Section: B Motivation For Tcam-based Classifier Compressionmentioning

confidence: 99%

Bit Weaving: A Non-Prefix Approach to Compressing Packet Classifiers in TCAMs

Meiners

Liu

Torng

2012

IEEE/ACM Trans. Networking

136

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Abstract-Ternary Content Addressable Memories (TCAMs) have become the de facto standard in industry for fast packet classification. Unfortunately, TCAMs have limitations of small capacity, high power consumption, high heat generation, and high cost. The well-known range expansion problem exacerbates these limitations as each classifier rule typically has to be converted to multiple TCAM rules. One method for coping with these limitations is to use compression schemes to reduce the number of TCAM rules required to represent a classifier. Unfortunately, all existing compression schemes only produce prefix classifiers. Thus, they all miss the compression opportunities created by non-prefix ternary classifiers.In this paper, we propose bit weaving, the first non-prefix compression scheme. Bit weaving is based on the observation that TCAM entries that have the same decision and whose predicates differ by only one bit can be merged into one entry by replacing the bit in question with *. Bit weaving consists of two new techniques, bit swapping and bit merging, to first identify and then merge such rules together. The key advantages of bit weaving are that it runs fast, it is effective, and it is composable with other TCAM optimization methods as a pre/post-processing routine.We implemented bit weaving and conducted experiments on both real-world and synthetic packet classifiers. Our experimental results show the following: (i) bit weaving is an effective stand-alone compression technique (it achieves an average compression ratio of 23.6%) and (ii) bit weaving finds compression opportunities that other methods miss. Specifically, bit weaving improves the prior TCAM optimization techniques of TCAM Razor and Topological Transformation by an average of 12.8% and 36.5%, respectively.

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Modeling TCAM power for next generation network devices

Abstract: Applications in Computer Networks

Cited by 99 publications

References 15 publications

Power Efficient IP Lookup with Supernode Caching

Power Efficient IP Lookup with Supernode Caching

A One-Shot Configurable-Cache Tuner for Improved Energy and Performance

Bit Weaving: A Non-Prefix Approach to Compressing Packet Classifiers in TCAMs

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