Power Efficient IP Lookup with Supernode Caching

Peng, Lü; Lu, Wencheng; Duan, Lide

doi:10.1109/glocom.2007.48

Cited by 10 publications

(7 citation statements)

References 10 publications

(9 reference statements)

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“…Furthermore, pipelined architectures increase the total number of memory accesses per clock cycle, and thus, increase the dynamic power consumption. The power dissipation in the memory dominates that in the logic [8,9,10]. Therefore, reducing memory power dissipation contributes to a large reduction in the total power consumption.…”

Section: Internet Protocol Packet Forwardingmentioning

confidence: 99%

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Prasanna

2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

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Section: Internet Protocol Packet Forwardingmentioning

confidence: 99%

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Prasanna

2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

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“…Furthermore, pipelined architectures increase the total number of memory accesses per clock cycle; and thus increase the dynamic power consumption. The power dissipation in the memory dominates that in the logic [16], [21], [15]. Hence, reducing memory power dissipation contributes to a large reduction in the total power consumption.…”

Section: Introductionmentioning

confidence: 99%

Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning

Prasanna

2012

IEEE Trans. Comput.

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Abstract-Memory efficiency and dynamically updateable data structures for Internet Protocol (IP) lookup have regained much interest in the research community. In this paper, we revisit the classic tree-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially arising in the next-generation IPv6 routing protocol. Due to longer prefix lengths and much larger address space, preprocessing such routing tables for tree-based LPM can significantly increase the number of prefixes and/or memory stages required for IP lookup. We propose a prefix partitioning algorithm (DPP) to divide a given routing table into k groups of disjoint prefixes (k is given). The algorithm employs dynamic programming to determine the optimal split lengths between the groups to minimize the total memory requirement. Our algorithm demonstrates a substantial reduction in the memory footprint compared with those of the state-of-the-art in both IPv4 and IPv6 cases. Two proposed linear pipelined architectures, which achieve high throughput and support incremental updates, are also presented. The proposed algorithm and architectures achieve a memory efficiency of 1 byte of memory for each byte of prefix for both IPv4 and IPv6. As a result, our design scales well to support either larger routing tables, longer prefix lengths, or both. The total memory requirement depends solely on the number of prefixes. Implementations on 45 nm ASIC and a state-of-the-art FPGA device (for a routing table consisting of 330K prefixes) show that our algorithm achieves 980 and 410 million lookups per second, respectively. These results are well suited for 100Gbps lookup. The implementations also scale to support larger routing tables and longer prefix length when we go from IPv4 to IPv6. Additionally, the proposed architectures can easily interface with external SRAMs to ease the limitation of on-chip memory of the target devices.

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“…The only work we found on using caching to reduce power consumption is [20] where some trie nodes are cached to skip the access to the deeper trie levels. However, such a scheme requires an external cache which results in extra power consumption.…”

Section: Related Workmentioning

confidence: 99%

Reducing dynamic power dissipation in pipelined forwarding engines

Jiang

Prasanna

2009

2009 IEEE International Conference on Computer Design

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Abstract-Power consumption has become a limiting factor in next-generation routers. IP forwarding engines dominate the overall power dissipation in a router. Although SRAMbased pipeline architectures have recently been developed as a promising alternative to power-hungry TCAM-based solutions for high-throughput IP forwarding, it remains a challenge to achieve low power. This paper proposes several novel architecture-specific techniques to reduce the dynamic power consumption in SRAM-based pipelined IP forwarding engines. First, the pipeline architecture itself is built as an inherent cache, exploiting the data locality in Internet traffic. The number of memory accesses which contribute to the majority of power consumption, is thus reduced. No external cache is needed. Second, instead of using a global clock, different pipeline stages are driven by separate clocks. The local clocking scheme is carefully designed to exploit the traffic rate variation and improve the caching performance. Third, a fine-grained memory enabling scheme is developed to eliminate unnecessary memory accesses, while preserving the packet order. Simulation experiments using real-life traces show that our solutions can achieve up to 15-fold reduction in dynamic power dissipation, over the baseline pipeline architecture that does not employ the proposed schemes. FPGA implementation results show that our design sustains 40 Gbps throughput for minimum size (40 bytes) packets while consuming a small amount of logic resources.

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Power Efficient IP Lookup with Supernode Caching

Cited by 10 publications

References 10 publications

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning

Reducing dynamic power dissipation in pipelined forwarding engines

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