A One-Shot Configurable-Cache Tuner for Improved Energy and Performance

Gordon-Ross,; Viana,; Vahid,; Najjar, Walid; Barros, Edna

doi:10.1109/date.2007.364686

Cited by 24 publications

(28 citation statements)

References 20 publications

(22 reference statements)

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“…Since our modeled system did not have a shared level two cache, and thus no dependencies between the instruction and data cache behavior, we evaluated separately the private level one instruction and data caches and used SimpleScalar [36] in order to obtain the cache accesses/hits/misses for each configuration for each application. We obtained off-chip access energy from a standard low-power Samsung memory, estimated that a fetch from main memory took forty times longer than a level one cache fetch, and the memory bandwidth was 50% of the miss penalty (44 cycles) [9]. …”

Section: Methodsmentioning

confidence: 99%

“…Figure 3 depicts our cache hierarchy energy model used for the instruction and data caches, which considered the dynamic and static energies [11]. We obtained the dynamic energy using CACTI [35] for 0.18-micron technology, estimated the static energy as 10% of the dynamic energy (a valid approximation for 0.18-micron technology [9]), and calculated the CPU stall energy to be approximately 20% of the active energy [9]. Since our modeled system did not have a shared level two cache, and thus no dependencies between the instruction and data cache behavior, we evaluated separately the private level one instruction and data caches and used SimpleScalar [36] in order to obtain the cache accesses/hits/misses for each configuration for each application.…”

Section: Methodsmentioning

confidence: 99%

“…Since during design space exploration, physically executing each explored configuration affects the application's runtime behavior, Gordon-Ross et al [9] proposed a non-intrusive oracle hardware that executed in parallel with the cache, evaluated all possible cache configurations simultaneously, and determined the best configuration. Even though this oracle hardware eliminated the performance overhead, the Oracle hardware imposed significant power and energy overheads and thus, was only feasible for systems with persistent applications to amortize these overheads.…”

Section: Design Space Explorationmentioning

confidence: 99%

“…To adhere to the application hardware requirements, much prior research focused on configurable hardware (e.g., [13][14][15][16][17][18][19][20][21][22][23]), configurable caches (e.g., [3,4,[24][25][26][27]), and design space exploration (e.g., [5][6][7][9][10][11][28][29][30][31][32]). Given this expansive prior work, we discuss fundamentals of configurable hardware, followed by specific related work in configurable caches and design space exploration with fundamentals that are directly applicable to our approach.…”

Section: Related Workmentioning

confidence: 99%

“…However, these methods incurred significant tuning overhead, including energy and performance overheads expended while executing the application in non-best configurations. To reduce the tuning overhead, other methods [8,9] measured the application's execution characteristics and used analytical models to predict the best configuration based on these characteristics. However, these methods required complex computations and lengthy calculation processing time [8], or high application persistency to amortize the tuning overhead [9].…”

Section: Introductionmentioning

confidence: 99%

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Low Effort Design Space Exploration Methodology for Configurable Caches

Alsafrjalani

Gordon‐Ross

2018

Computers

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Designers can reduce design space exploration time and efforts using the design space subsetting method that removes energy-redundant configurations. However, the subsetting method requires a priori knowledge of all applications. We analyze the impact of a priori application knowledge on the subset quality by varying the amount of a priori application information available to designers during design time from no information to a general knowledge of the application domain. The results showed that only a small set of applications representative of the anticipated applications' general domains alleviated the design efforts and was sufficient to provide energy savings within 5.6% of the complete, unsubsetted design space. Furthermore, since using a small set of applications was likely to reduce the design space exploration time, we analyze and quantify the impact of a priori applications knowledge on the speedup in the execution time to select the desired configurations. The results revealed that a basic knowledge of the anticipated applications reduced the subset design space exploration time by up to 6.6X.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Design Space Explorationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low Effort Design Space Exploration Methodology for Configurable Caches

Alsafrjalani

Gordon‐Ross

2018

Computers

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Introduction

Wang¹,

Mishra²,

Ranka³

2012

Dynamic Reconfiguration in Real-Time Systems

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Dynamic Cache Reconfiguration in Real-Time Systems

Wang

Mishra

Ranka

2012

Dynamic Reconfiguration in Real-Time Systems

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Research has shown that cache subsystem has become significant contributor in the overall energy consumption [78, 104]. Since different programs may have distinct requirements of cache configuration during execution, significant energy efficiency as well as performance improvements can be achieved by employing dynamic cache reconfiguration (DCR) in the system. Although reconfigurable caches are highly beneficial in general-purpose platforms [38,156], it has not been well studied in realtime systems due to several fundamental challenges. The first important question is how to employ and make efficient use of reconfigurable caches in such systems. Determining the appropriate cache configuration typically requires time-consuming evaluation of different candidate configurations. Furthermore, any change in cache configuration on-the-fly may arbitrarily alter task execution time. In hard real-time systems, the benefit of reconfiguration is limited since both of these facts can make scheduling decisions difficult and eventually may lead to unpredictable system behavior. However, soft real-time systems offer much more flexibility, which can be exploited to achieve considerable energy savings at the cost of minor impact in user experience.This chapter presents a novel methodology for applying cache reconfiguration in soft real-time systems with preemptive task scheduling. The proposed approach provides an efficient scheduling-aware cache tuning strategy based on static profiling and is applicable for both statically and dynamically scheduled soft real-time systems. Generally speaking, this technique is useful in any multitasking systems. The goal is to optimize energy consumption with performance considerations via reconfigurable cache tuning while ensuring that the majority of the task deadlines are met. We first consider single-level cache reconfiguration. As shown in [124], L1 cache energy consumption can be a significant part in overall energy optimization. In fact, some small embedded systems executing light-weight kernels are very likely to not even have L2 cache. This approach is independent of the actual cache sizes and is applicable for both large systems with larger L1 caches and small systems with smaller L1 caches. Next, we study dynamic cache reconfiguration in systems W. Wang et al.,

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A One-Shot Configurable-Cache Tuner for Improved Energy and Performance

Abstract: We

Cited by 24 publications

References 20 publications

Low Effort Design Space Exploration Methodology for Configurable Caches

Low Effort Design Space Exploration Methodology for Configurable Caches

Introduction

Dynamic Cache Reconfiguration in Real-Time Systems

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