Modeling single-event effects in a complex digital device

Clark, Kenneth A.; Ross, Alan A.; Loomis, H.H.; Weatherford, T.R.; Fouts, D.J.; Büchner, S.; McMorrow, D.

doi:10.1109/tns.2003.821793

Cited by 23 publications

(11 citation statements)

References 23 publications

(20 reference statements)

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“…The authors in [18] present a Monte-Carlo-based modeling program called SEMM. A methodology based on the single-event effect state transition model was developed in [19] to quantify the effect of SEUs on complex digital devices. Several methods proposed in the literature are based on models for transient fault injection and propagation [20]- [23].…”

Section: Prior Workmentioning

confidence: 99%

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Rao

Chopra

Blaauw

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs. In this paper, we present a fast and efficient soft error rate (SER) analysis methodology for combinational circuits. We first present a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit. We then describe the construction of the descriptor object that efficiently captures the correlation between the transient waveforms and their associated rate distribution functions. The proposed algorithm consists of operations to inject, propagate, and merge these descriptors while traversing forward along the gates in a circuit. The parameterized waveforms enable an efficient static approach to calculate the SER of a circuit. We exercise the proposed approach on a wide variety of combinational circuits and observe that our algorithm has linear runtime with the size of the circuit. The runtimes for soft error estimation were observed to be in the order of about 1 s, compared to several minutes or even hours for previously proposed methods.

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Section: Prior Workmentioning

confidence: 99%

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Rao

Chopra

Blaauw

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In the case of the test chips used in this study, all the errors were due to transients propagating through combinatorial logic chains. Several models have been developed to predict the error rate due to propagating transients in complex digital devices [5], [6]. Since in this study, only the transients themselves produce errors, the data reduction is much simpler.…”

Section: Introductionmentioning

confidence: 99%

Single event transient pulse widths in digital microcircuits

Gadlage

Schrimpf

Benedetto³

et al. 2004

IEEE Trans. Nucl. Sci.

124

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The radiation effects community has long known that single event transients in digital microcircuits will have an increasing importance on error rates as device sizes shrink. However separating these errors from static errors in latch cells has often proved difficult. Thus determining both the significance and the nature of these transient errors has not been easy. In this study, by utilizing a latch that is radiation hard at static clock frequencies the errors due to transients could be separated. By separating the transient error rate from the static upset error rate, the pulse structure of the propagating transients was studied using SPICE. The implications of these pulsewidths will also be discussed.Index Terms-Digital single event transients (DSETs), heavy ions, single event effects (SEEs), SPICE.

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“…It has a plateau region after a very short high-amplitude current peak when higher levels of charge are generated [31]. To deal with this issue, some voltage-dependent SET current models have been developed [30,[32][33][34].…”

Section: Set Modelmentioning

confidence: 99%

“…In this work, SET is generated by a voltage-dependent current model based on conventional double-exponential current pulse on the transistor taking into account the voltage across the node [34]. The current I inj (t) is defined by Equation (4), where V DS denotes the voltage between the drain and the source of the transistor.…”

Section: Set Modelmentioning

confidence: 99%

Voltage-Controlled Magnetic Anisotropy MeRAM Bit-Cell over Event Transient Effects

Maciel

Marques

Naviner

et al. 2019

JLPEA

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Magnetic tunnel junction (MTJ) with a voltage-controlled magnetic anisotropy (VCMA) effect has been introduced to achieve robust non-volatile writing control with an electric field or a switching voltage. However, continuous technology scaling down makes circuits more susceptible to temporary faults. The reliability of VCMA-MTJ-based magnetoelectric random access memory (MeRAM) can be impacted by environmental disturbances because a radiation strike on the access transistor could introduce write and read failures in 1T-1MTJ MeRAM bit-cells. In this work, Single-Event Transient (SET) effects on a VCMA-MTJ-based MeRAM in 28 nm FDSOI CMOS technology are investigated. Results show the minimum SET charge Q c required to reach the access transistor associated with the striking time that can lead to an unsuccessful switch, that is, an error in the writing process (write failure). The synchronism between the fluctuations of the magnetic field in the MTJ free layer and the moment of the write pulse is also analyzed in terms of SET robustness. Moreover, results show that the minimum Q c value can vary more than 100% depending on the magnetic state of the MTJ and the width of the access transistor. In addition, the most critical time against the SET occurrence may be before or after the write pulse depending on the magnetic state of the MTJ.

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Modeling single-event effects in a complex digital device

Abstract: Abstract-A methodology to quantify the impact of SEEs on complex digital devices has been developed. This methodology is based on the SEE State-Transition Model and was validated by radiation testing of a complex digital device.

Cited by 23 publications

References 23 publications

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Single event transient pulse widths in digital microcircuits

Voltage-Controlled Magnetic Anisotropy MeRAM Bit-Cell over Event Transient Effects

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