Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors

Abstract

Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs. In this paper, we present a fast and efficient soft error rate (SER) analysis methodology for combinational circuits. We first present a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit. We then describe the construction of the descriptor object that efficiently captures the correlation between the transient waveforms and their associated rate distribution functions. The proposed algorithm consists of operations to inject, propagate, and merge these descriptors while traversing forward along the gates in a circuit. The parameterized waveforms enable an efficient static approach to calculate the SER of a circuit. We exercise the proposed approach on a wide variety of combinational circuits and observe that our algorithm has linear runtime with the size of the circuit. The runtimes for soft error estimation were observed to be in the order of about 1 s, compared to several minutes or even hours for previously proposed methods.

Design as you see FIT: System-level soft error analysis of sequential circuits

“…If the glitch occurs in a combinational node, it can propagate and be latched in one or more downstream state elements. Depending upon the input vector applied to the circuit when the strike occurs, three masking factors can prevent the glitch from causing an upset in state [11] Timing masking of a single path can be resolved using an analytical approximation instead of exhaustive simulation [19,16,20]. The work of Krishnaswamy et al [10] and of Asadi and Tahoori [1] apply accurate unified analysis of timing and logical masking including multiple sensitized paths, but neglect electrical masking entirely.…”

“…This attenuation is often modeled using a parameterized representation of a glitch, and using transfer functions to describe its transformation as it propagates through logic [19]. Examples of parameterized glitch representations are pulse height and width [20], trapezoidal shaped waveforms [14], and Weibull functions [16]. While glitch attenuation is diminished in sub-100nm technologies [13,5], electri- cal effects are still important, as the FIT contribution of a gate depends strongly on its input states [16,7,20].…”

“…Based on the work of Hazucha et al [8] (and further adopted in [22,16]), the number of occurrences per 10 9 hours of a collected charge exceeding q, occurring at time t within the clock cycle is given by Eq. 5.…”

“…In either case, the neutron strike is modeled as a current of the form of Eq. 7 injected into a circuit node, as proposed by Freeman [6] and adopted in subsequent work [8,16,22]. Technologydependent parameter τ is the time constant of the injected current; τ is set to 20ps for both PMOS and NMOS devices in this work, as is shown to be appropriate for 90nm technology by Hazucha et al [8].…”

“…However, not all combinational nodes or state elements are affected equally. Prior work shows that the properties of combinational logic can result in the soft error rate differing by more than two orders of magnitude across state bits of a single design [16,22].…”