Design as you see FIT: System-level soft error analysis of sequential circuits

Holcomb, Daniel; Li, Wenchao; Seshia, Sanjit A.

doi:10.1109/date.2009.5090770

Cited by 34 publications

(18 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…the random variables in SWFI are only the stricken gate and the time of the SET). We compare the results of SWFI considering RWFI technique to investigate the accuracy of traditional FI techniques in evaluating the soft error vulnerability of the circuits [21][22][23]. Since, in a real environment, the SETs may have any probabilistic initial width (in a specific range) [5][6][7], RWFI is a more comprehensive and realistic approach and thus, is considered as the reference model hereinafter.…”

Section: Fault Injection Resultsmentioning

confidence: 99%

“…In dynamic approaches, SER estimation is typically achieved by injecting several SETs at the output of all susceptible gates and simulating the circuit using all possible input vectors. Although FI methods offer a high level of accuracy, they are very time-consuming and are not tractable for large-scale circuits [21,23,[29][30][31].…”

Section: Related Workmentioning

confidence: 99%

“…As an approach to find a metric in soft errors vulnerability analysis of digital circuits, static soft error rate (SER) estimation methods [14][15][16][17][18][19][20] have been extensively developed in addition to time-consuming simulation-based fault injection (FI) methods [21][22][23]. The general approach of the static SER estimation methods is as follows:…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A practical metric for soft error vulnerability analysis of combinational circuits

Raji

Pedram

Ghavami

2015

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Fault Injection Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A practical metric for soft error vulnerability analysis of combinational circuits

Raji

Pedram

Ghavami

2015

Microelectronics Reliability

View full text Add to dashboard Cite

“…The proposed approach is static in nature and dynamic input sequences (including closed loop feedback behaviour) are not considered. [18] proposes application of system level considerations in performing the safety evaluation, owing to substantial error masking occurring at higher design abstractions. The methodology employs fault injection on selected workloads for identifying the contribution of individual gates to the system level FIT.…”

Section: Background and Related Workmentioning

confidence: 99%

Improved Methods for Accurate Safety Analysis of Real-Life Systems

Prasanth

Parekhji

Amrutur

2015

2015 IEEE 24th Asian Test Symposium (ATS)

View full text Add to dashboard Cite

Integrated circuits are being used in different applications which are not always known at the time of specification and design creation. Safety standards specify that certain design processes be followed to guarantee safety of the applications in which these circuits are being used. As a result, the design phase is followed (often mandated) by an evaluation phase, wherein the safety worthiness of the circuit must be ascertained. In this paper, we perform a detailed study of such an evaluation as practised in the industry, understand the limitations, and propose techniques to improve the existing methodology. The improvements proposed are: (i) Capturing workload diversity as input constraints (values and sequence). (ii)Modelling application specific performance tolerance. (iii) Illustrating how physical system can be included into this analysis using a suitable representation. (iv) Budgeting of tolerance across various interacting modules to reduce computational complexity of safety analysis. Experimental results to illustrate suitability of the proposed methods are presented using a set of ITC benchmark circuits and two representative industrial circuits.

show abstract

“…Circuit level analysis techniques [3,4] are applied to the flattened netlists and hence, lose the abstraction efficiency of error analysis and mitigation at RTL, as the useful high level behavioral semantics are ignored.…”

Section: Introductionmentioning

confidence: 99%

Quantitative evaluation of register vulnerabilities in RTL control paths

Chen

Ebrahimi

Tahoori

2014

2014 19th IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

Radiation-induced soft error is a significant reliability issue in nanoscale technology nodes. In this paper, a novel approach based on probabilistic model checking is proposed to quantify the soft error vulnerabilities of the registers in the control paths at the Register-Transfer Level (RTL). Efficient abstraction and model simplification techniques are proposed to significantly improve the scalability of our method. The experimental results show the effectiveness of proposed techniques to successfully quantify the register vulnerabilities in the RTL design, to be used for cost-effective selective register protection. I. INTRODUCTIONSoft error induced by radiation effects is a significant reliability concern in nanoscale VLSI design, and sequential elements (flip-flops) are the dominant contributors to the overall system soft error rate [1]. Accurate analysis of their vulnerabilities plays a key role in selective protection schemes.The architecture level evaluation techniques mostly rely on architecturally correct execution analysis and are not applicable to irregular structures such as the controllers with sequential elements [2]. Circuit level analysis techniques [3,4] are applied to the flattened netlists and hence, lose the abstraction efficiency of error analysis and mitigation at RTL, as the useful high level behavioral semantics are ignored.In the typical RTL designs, the error propagation and masking analysis in control paths are much more challenging than that in data paths. In addition, the control signals may manifest much non-uniform probabilities due to different workloads. For soft error evaluation work at the RTL, fault injections [5] require a long simulation time to obtain results with a reasonable accuracy. A model-checking based technique is employed in [6] to identify the registers that must be protected for correct system functionality, but it only provides a binary classification (yes/no) rather than a quantitative metric.In this paper, we propose a novel method based on formal Probabilistic Model Checking (PMC) to quantitatively evaluate register vulnerabilities in the RTL control paths, therefore avoid time-consuming statistical fault injection. We model the probabilistic behaviors of the RTL designs as Discrete Time Markov Chains (DTMCs), and take workload dependencies into consideration. Furthermore, we leverage the RTL behavioral semantics and exploit several abstraction and simplification techniques to exponentially reduce the size of the state space. The experiment results show that the proposed method is able to handle complex control modules in a typical embedded processor.

show abstract

Design as you see FIT: System-level soft error analysis of sequential circuits

Cited by 34 publications

References 23 publications

A practical metric for soft error vulnerability analysis of combinational circuits

A practical metric for soft error vulnerability analysis of combinational circuits

Improved Methods for Accurate Safety Analysis of Real-Life Systems

Quantitative evaluation of register vulnerabilities in RTL control paths

Contact Info

Product

Resources

About